EXPERIMENTAL SOFTWARE RECEIVER O F SIGNALS OF SATELLITE NAVIGATION SYSTEMS

3. EXPERIMENTAL SOFTWARE RECEIVEROF SIGNALS OF SATELLITE NAVIGATION SYSTEMS František VEJRAŽKA, Pavel KOVÁŘ, Libor SEIDL, Petr KAČMAŘÍK Czech Technical University in Prague Department of Radio Engineering Technická 2, 166 27 Praha 6, Czech Republic Phone: +420 2 2435 2246, fax +420 2 2435 5829 vejrazka@fel.cvut.cz

4. AGENDA • Introduction • Receiver architecture • Receiver software architecture • Validation project • Validation results • Future plans • Conclusion

5. INTRODUCTION • Task: Participation of the Czech Republic in GALILEO project • It needs: Different algorithms dependent on implementation character EXPERIMENTAL RECEIVER FOR SATELLITE NAVIGATION

6. INTRODUCTION Contribution describes: • Experimental receiver as a tool for research in GNSS • processing of the signals of present and future GNSS • GNSS signal processing algorithms development and testing • Validation of the receiver • architecture • hardware • FPGA development method • SW development flow • implementation GPS L1 CA code receiver

7. AGENDA • Introduction • Receiver architecture • Receiver software architecture • Validation project • Validation results • Future plans • Conclusion

8. RECEIVER ARCHITECTURERequirements • Processing of all known and planned SATNAV signals: • GPS L1, L2, L5 • GLONASS • EGNOS, WAAS • GALILEO • Flexible design and development of powerful algorithms of signal processing • Easy implementation of them • Rapid and simple prototyping and testing  Software Defined Radio 

9. RECEIVER ARCHITECTURE • Radio Frequency unit • DSP Unit • High Power Computer

10. RECEIVER ARCHITECTURE • Radio Frequency Unit • DSP Unit • High Power Computer • Parameters: • frequency band 1 – 2 GHz • bandwidth 2 - 35 MHz adjustable • frequency tuning step 100 kHz

11. RECEIVER ARCHITECTUREHardware Radio Frequency Unit realization

12. RECEIVER ARCHITECTURE Hardware Radio Frequency Unit realization in 19“ rack

13. RECEIVER ARCHITECTURE • Radio Frequency unit • DSP Unit • High Power Computer • Parameters: • two 14 bits A/D converters • sample frequency up to 65 MHz • sufficient computational power for 40 MHz bandwidth

14. RECEIVER ARCHITECTUREDSP UnitSoftware design flow

15. RECEIVER ARCHITECTURE • Radio Frequency unit • DSP Unit • High Power Computer • Parameters • PC computer with WINDOWS 2000 OS • planed: Embedded RT Kernel • multithread software

16. AGENDA • Introduction • Receiver architecture • Receiver software architecture • Validation project • Validation results • Future plans • Conclusion

17. RECEIVER ARCHITECTUREHigh Power Computer (HPC) UnitSoftware architecture • modularity, portability • ANSI C/C++ • multithreading • interproces communication through shared memory • multiplatform solution • PC (i686) • system Win32, Linux • Embedded application (Virtex II-Pro - PPC-405) • Real-Time kernel (Micro-C)

18. RECEIVER ARCHITECTUREHigh Power Computer (HPC) UnitSoftware library structure • Channel handling and control • Raw measurement processing • filtration • verification (RAIM) • Data demodulation and interpretation • Satellite position determination • Coordinate transformation • Atmospheric correction • User position estimation and verification • System integrity monitoring • System augmentation of differential measurement • User interface

19. AGENDA • Introduction • Receiver architecture • Receiver software architecture • Validation project • Validation results • Future plans • Conclusion

20. VALIDATION PROJECT • Validation of the receiver • architecture • hardware • FPGA development method • SW development flow • Implementation GPS L1 CA code receiver

21. User interface User interface User interface VALIDATION PROJECT Implementation GPS L1 C/A code receiver Radiofreq. part Data demodulation Data interpretation and archiving Array of channels (Virtex II) Raw measurement conversion Position determination System integrity monitoring Channels handling and control Search and tracking

22. VALIDATION PROJECTDSP UnitImplementation GPS L1 C/A code receiver Correlator structure

23. VALIDATION PROJECTDSP UnitImplementation GPS L1 C/A code receiver Correlator realization

24. VALIDATION PROJECTDSP UnitImplementation GPS L1 C/A code receiver Correlator realization 32 bits NCO and PRN generator of GPS and EGNOS codes

25. VALIDATION PROJECTDSP UnitImplementation GPS L1 C/A code receiver Correlator realization 32 bits NCO and complex (IQ) mixer 32 bits NCO and PRN generator of GPS and EGNOS codes

26. VALIDATION PROJECTDSP UnitImplementation GPS L1 C/A code receiver Correlator realization - state diagram of the correlator service routine

27. AGENDA • Introduction • Receiver architecture • Receiver software architecture • Validation project • Validation results • Future plans • Conclusion

28. Early – Late envelope estimation of the mean envelope level (dot) Code delay error In phase and Quadrature output of the correlator Frequency error Phase error

29. Early – Late envelope estimation of the mean envelope level (dot) Code delay error In phase and Quadrature output of the correlator Frequency error Phase error

30. Early – Late envelope estimation of the mean envelope level (dot) Code delay error In phase and Quadrature output of the correlator Frequency error Phase error

31. Early – Late envelope estimation of the mean envelope level (dot) Code delay error In phase and Quadrature output of the correlator Frequency error Phase error

32. Early – Late envelope estimation of the mean envelope level (dot) Code delay error In phase and Quadrature output of the correlator Frequency error Phase error

33. Early – Late envelope estimation of the mean envelope level (dot) Code delay error In phase and Quadrature output of the correlator Frequency error Phase error

35. AGENDA • Introduction • Receiver architecture • Receiver software architecture • Validation project • Validation results • Future plans • Conclusion

36. FUTURE PLANS • Implementation of GPS L2 CA code • Diversity reception of EGNOS • Implementation of Galileo

37. GPS L1 C/A code GPS code based positioning DGPS EGNOS GPS L2 C/A code GPS + GLONASS GPS L1/L2 P-code GPS + EGNOS GLONASS GPS + GALILEO GALILEO Realized and planed tasks Signal processing Positioning methods

38. Problem:signal reception in hard conditions • under leaves canopy • in hollowed tracks • in street canyons • inside buildings • etc. Solution: Assisted GNSS (AGNSS)

39. FUTURE PLANS • Implementation of GPS L2 CA code • Diversity reception of EGNOS • Implementation of Galileo • AGPS

40. AGENDA • Introduction • Receiver architecture • Receiver software architecture • Validation project • Validation results • Future plans • Conclusion

41. CONCLUSION • Experimental receiver was validated • Architecture of the receiver was confirmed • Complete development process of the application was verified • Performance of the FPGA was approved • Experimental receiver is ready for implementation of the new GNSS signals and for signal processing

42. Thank you for your attention.Pavel Kovář & František Vejražka & Libor SeidlCzech Technical UniversityPraguehttp://radio.feld.cvut.cz/personal/vejrazka