Incorporating Driver Sizing Into Buffer Insertion Via a Delay Penalty Technique

Incorporating Driver Sizing Into Buffer Insertion Via a Delay Penalty Technique Chuck Alpert, IBM Chris Chu, Iowa State Milos Hrkic, UIC Jiang Hu, IBM Stephen Quay, IBM Gopal Gandham, IBM Chandramouli Kashyap, IBM

Which One is Not Like the Others?

Buffer insertion Wire sizing Driver sizing Steiner tree Which One is Not Like the Others? BIWS

Electrically-challenged net Driver sizing alone Buffer insertion alone Simultaneous optimization Why Simultaneous Optimization?

Three choices Integrating Driver Sizing

slow stage Driver Sizing Affects Multiple Nets

Upstream Capacitance Effects Slack (ns) # Nets Optimized

C1 C2 Decoupling buffers C1 The Driver Sizing Penalty Penalty is delay through fastest decoupling buffer/inverter chain

Delay Penalty Algorithm • Continuous buffer library not realizable • Assume • set of discrete buffers B1, . . ., Bn such that CB1< CB2< . . . < CBn • monotone function delay(Bi, C) • Apply dynamic programming

Given optimal chains Find optimal chain for B5 B1 B2 CB5 B3 B4 Example

Dynamic Programming Recurrence • To drive capacitance CBi, combine optimal chain driving CBj with buffer Bj • D(CB1)=0 • D(CBi)=min0<j<i{D(CBi) + Delay(Bj, CBi)}

Advantages • O(n2) complexity • Compute once as a lookup table • Can handle inverters and slew • Virtually no CPU cost • Applicable for many approaches

Experiments • Five unoptimized circuits (73 – 303K cells) • Three approaches • VG (no driver sizing) • Max (driver sizing with no delay penalty) • DP (driver sizing with delay penalty) • Run on thousands of nets

Total Buffers Inserted

Number of Upsized drivers

Total Area Percentage Increase

Worst Slack

And So . . . • Simple to combine buffer insertion with driver sizing • Virtually no CPU impact • Extends to many buffer insertion approaches • No timing graph queries • Works well

Incorporating Driver Sizing Into Buffer Insertion Via a Delay Penalty Technique