CMOS VLSI DESIGN

1. CMOS VLSI DESIGN Kasin Vichienchom kvkasin@kmitl.ac.th Lecture#2

2. D D B G B G S S Body Effect • Threshold Voltage is a function of VSB NMOS VT > 0 D B G S VT > VTO VT = VTO VT < VTO

3. Body Effect • Negative bias on substrate causes the threshold of NMOS increases from 0.45 V to 0.85 V (Source: Rabaey)

4. Body Effect • Threshold Voltage is a function of VSB PMOS VT < 0 S S G B G B G B D D D |VT| = |VTO| |VT| > |VTO| |VT| < |VTO|

5. M1 M1 M2 M2 M3 M3 Body Effect Example stacks of NMOS and PMOS VT1 > VT2 > VT3 |VT1| < |VT2|< |VT3|

6. MOS Model in SPICE • Based on device physics and empirical equations • Several generations of model was developed according to the advance in process technology for example: • Level 1 (quadratic model) • Level 2, Level 3 … • EKV • BSIM1, BSIM2, BSIM3 (Level 49) • Model Parameters are related to: • Physical Process technology parameters such as tox, xj, μ • Electrical parameters such as VT, γ, λ

7. MOS Model in SPICE Example: NMOS Level1 model parameters from parameter extraction the following values are determined • Thus the corresponding SPICE Level1 parameter are: • VTO=0.5 V, KP = 300e-6, PHI=0.8, • GAMMA=0.4 an LAMBDA=0 • Input file for SPICE simulation will have: • .model NMOS level1 vto=0.5 kp=300u phi=0.8 gamma=0.4 + lambda=0

8. Model Parameters Example BSIM3 (Level 49) (Source: MOSIS TSMC 0.18µ)

9. SPICE input file • Example: IV Characteristic of NMOS • **Setting Parameters and Model Library** • .param Supply=1.8 *Set value of Vdd • .lib ‘bsim3v3.cmos.18um’ *Set 0.18um library • .opt scales=0.1u • **Circuit Netlist** • M1 2 1 0 0 cmosn l=1 w=4as=20 ps=20 pd=4 • Vdrain 2 0 ‘Supply’ • Vgate 1 0 ‘Supply’ • **Analysis Setup** • .dc Vdrain 0 ‘Supply’ ‘Supply/20’ Vgate 0 ‘Supply’ ‘Supply/4’ • .plot dc I(M1) • .end

10. Additional Effects in MOS transistors • Parameter Variations in Production • Keys parameters are L, VT and tox • The model library based on the extremes of the key parameters is called Process Corners • Typical (nominal) • Fast • Slow Design Corners: An imaginary box that surrounds the guaranteed performance of the circuits (Source: Weste)

11. Additional Effects in MOS transistors • Temperature Effects As temperature increases: • Mobility will decrease (and so the drive current) • Threshold voltage will decrease • Subthreshold current will increase due to increasing in minority carrier concentration

12. Temperature Dependence • Combination of temperature effects • As temperature increase: • on current decrease • off current increase (Source: Weste)

13. Short Channel Threshold Voltage Short Channel Effect (SCE): As L decreases, depletion regions of source and drain move closer together and actually aid in depletion process of the channel. Reverse Short Channel Effect (RSCE): Due to oxidation-enhanced diffusion (Source: D. Hodges)

14. Short Channel Threshold Voltage • Drain-induced barrier lowering (DIBL) • Drain-Source voltage assists Gate voltage in depletion process. (Source: D. Hodges)

15. DC Voltage Transfer Characteristic Ideal VTC of an INV (Source: D. Hodges)

16. CMOS Inverter VTC

17. Noise Margin Definition (Source: Weste)

18. CMOS Inverter DC analysis • VGSN = VIN • VDSN = VOUT • |VGSP| = VDD-VIN • |VDSP|= VDD-VOUT • IDSP = IDSN

19. CMOS Inverter Graphical Method (Source: Weste)

20. CMOS Inverter Region (A) VIN< VTNNMOS off, PMOS onin LinearIDS = 0 Vout = VDD = VOH and VDSP = Vout – VDD = 0 Region (B) As VIN > VTN NMOSoninSat since VDSNis still larger than VGS-VTN.PMOS is on in linear and current starts to flow from VDD to GND. Region (C) As VIN increases more, both PMOS and NMOS enter Saturation mode. A large amount of current, IDD flows. Region (D) VDD/2 < VIN < VDD - |VTP| NMOS changes to Linear mode while PMOS is still inSat. The amount of current is reduced Region(E) As VIN > Vdd - |VTP|, PMOScut offno current flows. NMOS is inLinear mode connecting output to GND therefore VOUT = GND = VOL

21. CMOS Inverter (Source: Weste)

22. CMOS Inverter Analysis • To compute VOH, VOL, and VS , consider • n-off p-lin: VOUT = VOH = VDD; IDS = 0 • (B) n-sat p-lin: IDN(sat) = IDP(lin) ---(1) substituteVIN to findVOUT • (C) n-sat, p-sat: IDN(sat)=IDP(sat) ---(2)

23. CMOS Inverter Analysis • To computeVS (switching voltage) assumeVS≈VDD/2 henceVin –VTN <<ECN andVDD – Vin -|VTP| << ECPLP ifVTN ≈ VTP andχ= 1 thenVS≈ VDD/2

24. Vout NMOS strong PMOS strong Vin CMOS Inverter Analysis χ< 1, VS<VDD/2 χ> 1, VS>VDD/2 χ= 1 VS≈ VDD/2

25. CMOS Inverter Analysis • (D) n-lin, p-sat: IDN(lin) = IDP(sat) ---(3) substituteVIN to find VOUT • (E) n-lin, p-off: VOUT = GND = VOL

26. CMOS Inverter Analysis • VIL occurs in (B) thus use(1) by assuming : • Vin-VTN << ECNLN and VDD-Vout << ECPLP yields and substitute ---(4)

27. CMOS Inverter Analysis Then diff (4) w.r.t. VIN and substitutes replaceVIN withVIL and solve for VIN: ---(5) Use (5) and (4) to eliminate VOUT and find VIL

28. CMOS Inverter • VIH ocurrs in(D) therefore use(3) by assuming : • VDD-Vin-|VTP| << ECPLPและ Vout << ECNLN yield and use ---(6) Then diff (6) w.r.t. VIN and substitutes replaceVIN withVIL and solve for VIN: ---(7) Use (7) and (6) to eliminate VOUT and find VIH

29. CMOS Inverter: RC Delay Step Input Vin = VDD Vin = GND

30. CMOS Inverter: RC Delay tPHL ≈ 0.69RNCL tPLH ≈ 0.69RPCL

31. CMOS Inverter: RC Delay Equivalent Resistance Therefore const = Ron of MOS that has W = L i.e. “unit-sized” MOS • unit-sized NMOS has on-resistance of 12.5 k • unit-sized NMOS has on-resistance of 30 k These values are approximately correct for a number of different technologies including 0.35µm 0.18µm and 0.13µm

32. CMOS Inverter: RC Delay Unit-sized MOS 7 units 2 units

33. CMOS Inverter: Sizing • According to switching voltage • prefer to have VSW = VDD/2 • According to propagation delay • Prefer to have tPHL = tPLH