ITS BUS : INNER MODULE

1. ITS BUS : INNER MODULE Antoine JUNIQUE

2. Introduction • ITS_BUS layout • ITS_CHIP pin-out • Differential impedance • Voltage drop • Current flow • Power plane impedance • S-Parameter • Channel simulation Antoine JUNIQUE

3. ITS_FLEX_CABLE layout 280.8 mm 15 mm Fig 1: ITS Flex Cable size 4 mm 3.5 mm 25 µm ALUMINUM AVDD DVDD CHIP 9 100 µm Pyralux AP CHIP 8 25 µm ALUMINUM AGND DGND CHIP 7 4 mm 10.7 mm CHIP 6 Fig 2: ITSFlex CableLayer stackup CHIP 5 CHIP 4 CHIP 3 AVDD CHIP 2 AGND DVDD CHIP 1 DGND Fig 4: Fig 3: Antoine JUNIQUE

4. ITS_CHIP ITS_CHIP AVDD AGND DGND CLK DVDD NC Tab 1: ITS chip pinout DATA OUT DATA IN / OUT Fig 4: ITS chip pinout Antoine JUNIQUE

5. ITS_CHIP DATA OUT 30 mm CLK DATA IN/OUT DATA OUT 2 mm 3.5 mm 1 mm Ø0.2 mm 6 mm DGND 15 mm 2.2 mm DVDD 2.2 mm AGND 2.2 mm AVDD Fig 6: ITS silicon chip, bottom view ITS_CHIP_V3_3 (ITS_15_30_HOLE_02MM_V2) 4 mm Antoine JUNIQUE

6. Differential impedance (Q3D extractor 10) A A A B B B PYRALUX_AP Tab 8: Zdiff_80_80_al_nocl_PyraluxAP Tab 7: Zdiff_100_100_al_nocl_PyraluxAP Tab 9: Zdiff_50_50_al_nocl_PyraluxAP X = 100 µm X = 80 µm X = 50 µm X µm X µm X µm A B 25 µm Fig 7: Layer stackup 7 lines width Antoine JUNIQUE

7. DC Voltage Drop (Siwave 8) Fig 7: Power plane, AVDD & DVDD DC Voltage drop Fig 8: Ground plane, AGND & DGND DC Voltage drop Voltage sources AVDD Current sinks DVDD Fig 9: Power plane, AVDD & DVDD Antoine JUNIQUE

8. DC Voltage Drop (Siwave 8 & Excel) Tab 3: Analog voltage Fig 10: Drop voltage along the flex cable Tab 4: Digital voltage Antoine JUNIQUE

9. DC Voltage Drop (Siwave 8 & Excel) Chip9 Chip7 Chip8 Chip6 Chip5 Chip4 Chip3 Chip2 Chip1 Fig 11: Drop voltage sees by each ITS chip Antoine JUNIQUE

10. Current density (Siwave 8) Fig 12: Power plane, AVDD & DVDD current density Fig 13: Ground plane, AGND & DGND current density Voltage sources AVDD Current sinks DVDD Fig 14: Power plane, AVDD & DVDD current density Antoine JUNIQUE

11. Power plane impedance (Siwave 8) Impedance (Ohms) Fig 15: impedance of the DVDD as seen from the chip9 without decoupling capacitor Fig 16: Resonant Mode Analysis Antoine JUNIQUE

12. Power plane impedance (Siwave 8) Without capacitors Impedance (Ohms) With capacitors Fig 17: impedance of the DVDD as seen from the chip9 without & with decoupling capacitor Antoine JUNIQUE

13. S-PARAMETER (Siwave 8) Fig 18: Differential transmission line 9 Insertion loss vs substrate thickness Fig 19: Differential transmission line 9 Return loss vs substrate thickness Antoine JUNIQUE

14. S-PARAMETER (Siwave 8) Export touchstone file for PI & SI: Add points at low frequency to achieve a good state space fit. Fig 20: Siwave SYZ parameters Frenquency Range Setup Antoine JUNIQUE

15. Channel simulations (Designer 8) Fig 21: Designer schematic Antoine JUNIQUE

16. IBIS ECL buffers issue (Designer 8) Fig 22: IBIS model issue Antoine JUNIQUE

17. PDN NOISE voltage & current (Designer 8) Fig 23: PDN noise, Voltage & Current without decoupling capacitor. Antoine JUNIQUE

18. Step response (Designer 8) Fig 24: Differential transmission line 9 step response @ 2Gb/s Antoine JUNIQUE

19. PRBS response (Designer 8) Fig 25: Differential transmission line 9 PRBS response @ 2Gb/s Antoine JUNIQUE

20. EYE DIAGRAM (Designer 8) Eyediagramme with longest diff line (260mm) @ 2Gb/s. Differential impedance 62 Ohms (sub 25µm) Differential impedance 102 Ohms (sub 65µm) Differential impedance 117 Ohms (sub 100µm) Antoine JUNIQUE

21. VerifEye Contour & VerifEye Bathtub (Designer 8) BER = 10-12 Fig 30: QuickEye 2D Bathtub @ 2Gb/s Fig 29: VerifEYE Contour Plot @ 2Gb/s Antoine JUNIQUE

22. Summary • Power Integrity Techniques using Q3D, Siwave 8 and Designer 8 presented: • Differential impedance • DC-IR Drop • Power plane impedance and resonances • S-Parameter Extraction • System level: PDN noise, Step response, PRBS response, EYEdiagram, BER. Antoine JUNIQUE

23. Q & A Antoine JUNIQUE