The Chip Design Crisis

The Chip Design Crisis Univ.-Prof. Dr.-Ing. Markus Rupp June,2 2008

Outline • Why Mobile Communications? • Problems in the Design of Wireless Systems • Complexity Gap • Design Productivity Gap • Problems and Solutions • Parallelism, IP-Reuse, Predictive Design • Inconsistent Design, Lack of Tool Support, Refinement Techniques, Design Languages, Automatic HW/SW Partitioning • Virtual Prototyping, Automatic Testing and Verification, Automatic Float to Fix Conversion • Static Code Analysis, automatic DFG and CFG Generation, Code Understanding and Interpretation • Low Power and Power aware Designs • Software Defined Radio • Conclusions

Why Mobile Communications? • Communication is a deep, human requirement • In particular in oral form • We would like to speak with arbitrary persons any time at any location.

Mobile communication of the past • C-Netz Autotelefonnetz C • Start Nov.1984 • First only in automobiles (later portable 10 kg) • Starting price ca. 50.000 öS • First fully automatic mobile cellular net (radius about 15 km)

How do we communicate today? • GSM • Developed to support speech only (intro Austria in 94) • Although, today also SMS (in Austria 95) and with GPRS also data transmission possible. • UMTS • Supports equally speech and various data services • Even Multimedia Application with Video Streaming • WLAN • Originally planned as pure data communication (Internet) • Supports also speech services (VoIP)

Is Mobile Communication successful? Until selling of one Million units, it took…

Is Mobile Communication successful?http://www.rtr.at/en/tk/TeilnehmerstaendeMF2007 9,7 9,6 8,4 User in Austria in Millions 2006 2006 2005

What makes Mobile Communications a difficult task? • Limited Spectrum • Most of Spectrum is used by ORF!

Spectrum

What makes Mobile Communications a difficult task? • Limited Spectrum • Most of Spectrum is used by ORF! • Limited Battery Power • Battery increases with 2% per year

Power Handy requires only 0,000 000 000 000 1 Watt for reception!

What makes Mobile Communications a difficult task? • Limited Spectrum • Most of Spectrum is used by ORF! • Limited Battery Power • Battery increases with 2% per year • Multi-path propagation

Multi Path Propagation

What makes Mobile Communications a difficult task? • Limited Spectrum • Most of Spectrum is used by ORF! • Limited Battery Power • Battery increases with 2% per year • Multi-path propagation • Complexity

Complexity Gap in 3rd G. Wireless Processor Performance (Moore)

Design Productivity Gap Transistors per Chip (M) Productivity Trans./Staff - Mo. 10,000 100,000,000 1,000 10,000,000 .10m 58%/Yr. compound Complexity growth rate 100 1,000,000 10 100,000 .35m 1 10,000 x x 1,000 .1 x x x x x x 100 21%/Yr. compound Productivity growth rate .01 2.5m 10 .001 1991 1999 2001 2003 2007 1989 1993 1995 1997 2005 2009 1983 1985 1987 1981 Logic Tr./Chip Source: SEMATECH Tr./S.M.

Some Observations in 3rd Generation Wireless • Today, about 70% of development time is verification. • 90% of the product cost are predetermined by its detailed specification. • Standards (UMTS R99 in Dec.1999, R4 in March 2001,R5 in March 2003, R6 (Dez 04), R7 (Sep 05), R8 (Nov 07?). change faster than the product design cycle. • The required time to market becomes decisive: launching six months early, triples profits, six months late results in breaking even.

Sematech‘s Answer (1999) • For every $1 invested in EDA tools, an additional $2 to $5 are spent on integration into the design flow. • No EDA vendor or using company can supply all the tools needed today. • Promote rapid integration of new tools from industry and university research. • Create Chip Hierarchical Design System technical standard (CHDStd) • This has not happened until today!

Problems and Solutions • Solutions to the Complexity Problem: • Predictive Design • Parallelism • Hardware Accelerators • Re-using IP • = “Classical Approaches”

Problems and Solutions • Solutions to the Design Productivity Problem: • No Solutions currently in Products • Multitude of Problems exist:

System-Design Marketing Research Implementation Inconsistent Design

High Level of abstraction Low Lack in Tool Support Ptolemy

Lack in Tool Support • A multitude of EDA Tools exists already . • However, they all cover only a certain part of the design flow. • Major disadvantage of existing EDA Tools: not compatible to each other! • Basic lack exists in: • HW/SW/FW partitioning • Platform based designs • Float-to-Fix conversion • Power aware design at High Level description

Dream: Consistent Design Flow

Dream: Consistent Design Flow • Can be achieved... • Via a single design representation covering all design steps equally • Via one-code paradigm • Via refinement steps • Via closing the tool gap...

Open Tool Integration Environment (OTIE)

Design Database (DBB) Internal View • For static code analysis • property tables, • process table, • and basic block tables • of the DDB are used.

Automatic HW/SW Partitioning Example Delay Profile Estimator (a UMTS receiver component) Cost = ρCostCC + (1- ρ) CostGC ρ = 0.68 .. 0.7 We basically achieved the same result as well-trained design group We needed about 6 seconds!

Algorithmic Design Architectural Design HW Realisation SW Implementation FW Development Algorithmic Design Architectural Design VP Implementation HW Realisation SW Implementation FW Development Algorithmic Design Architectural Design VP Implementation HW Realisation SW Implementation FW Development Virtual Prototyping (1)

HW/SW Interface VP Virtual Prototyping (2) • Virtual Prototype: • Whole system behavior can be tested via simulation • but not as fast as having a prototype available • After HW is available, VP can be replaced SW/FW HW

System bus Direct I/O Supporting Platform Based Designs in VP . . . DMA DSP RAM . . . HA1 HA2

Automatic VP Generation Environment

Results of Industrial Deployment Design effort for manual VP creation [Person-hours] Total = 144 person-hours A matter of seconds!!!

Verification (1) Today, about 70% of development time is verification

Verification (2) • With such high complexity, a complete verification on every level is not possible! • The higher the design level, the faster the simulation time • Run all but one module (DUT) on highest possible design levels. • Generate test vectors automatically for all design levels.

Direct I/O Bus Automatic Test Pattern Reuse Registers Memory HA1 HA2 Memory image …  DSP DMA C test program

Float SDI Generation Optimisation Hybrid Evaluation Float/Fixed Conversion Environment SSD SSD

Float to Fix Conversion Results {16} {8,16,32}

Float to Fix Conversion Results

Process Graph Representation Process (CFG) Basic Block (DFG) a b c z • Process is represented as CFG • One Basic Block consists of a DFG

Control Flow Graph of an FIR Filter

CFG Example • E.g. function of aDelay Profile Estimator • Basic Blocks and function are annotated with properties • Operations +,-,* • Control if, jmp • Loop counter

7 - 20X 2 – 5X 20 – 50 % Power Aware Design POWER REDUCTION OPPORTUNITIES SYSTEM LEVEL BEHAVIORAL LEVEL RT LEVEL LOGIC LEVEL TRANSISTOR LEVEL LAYOUT LEVEL

Power Reduction • Dynamic Methods • Sleep modes • Dynamic frequency scaling (DFS) • Dynamic voltage scaling (DVS) • Reducing Switching Activity • Clock gating • Minimization of glitches • Reducing number of operations • Adapting Process Technology • Reducing capacitance • Reducing leakage current • Reducing supply voltage

Software Defined Radio • What is the next step in direction automatic chip design? • Software design is cheaper than Hardware design (also faster). • Why not designing a new and very flexible HW platform, so flexible that algorithmic descriptions can directly be run on it runtime reconfigurable HW?

The Chip Design Crisis