Report on the first Gigatracker chip design meeting

1. Report on the first Gigatracker chip design meeting

2. Where, when, who • Torino, 21.03.2006 • People attending the meeting: • Ferrara: A. Cotta Ramusino, R. Malaguti • Torino: A. Rivetti, G. Mazza, S. Martoiu, A. La Rosa • CERN: A. Kluge, S. Tiuraniemi, G. Anelli Giovanni Anelli - CERN

3. First important decision taken • We made the choice of using a 0.13 um CMOS technology. The main reasons behind the choice are: • The 0.25 um technology might not be available to us at the time of production of the chip; • The design kit of the 0.25 um technology is not maintained anymore; • The 0.13 um technology will be available to us for many years in the future; • The 0.13 um technology offers a superior performance for digital circuits; • Most of the problems of using this technology are solved or being solved: more and more people in the community are using it, a design kit is going to be prepared soon, CERN will have a frame contract with a vendor and will organize frequent MPWs as it has been done for the 0.25 um technology in the past. Giovanni Anelli - CERN

4. Second important decision • We plan to submit a test chip containing several test structures and basic blocks in August – October 2006. An exact date has not been fixed yet, this depends also on the outcome of CERN’s call for tender. One option could be to submit a 10 mm^2 chip on the 7th of August through Mosis (IBM 0.13 um LM technology). • We decided to share the responsibilities as follows: • Preamplifier: Giovanni A., Angelo R., maybe Sakari T.; • Current mode CFD: Sorin M.; • One TDC per pixel: Angelo R., Sorin M.; • Time over threshold: Alex K., Giovanni A.; • CFD: Angelo C.R., Roberto M., Stefano C.; • General architecture, trigger: Alex K., Gianni M.; • T.D.C.: Gianni M., Sakari T.; • Substrate noise: Sakari T., Giovanni A.; • LVDS buffers: Sakari T.; • RC delay and jitter in lines: Angelo C.R., Roberto M., Stefano C. Giovanni Anelli - CERN

5. Issues still under discussion • Time-walk cancellation is a very critical issue to get the necessary timing resolution. This is also why we will investigate in parallel several possibilities (2 CFD architectures and TOT); • In the first test chip we might not be using enclosed transistors, if this gives problem with the extraction. Nevertheless, all the designs have to be made keeping in mind the limitations of using ELTs; • LVDS drivers: what is the C of what we are going to drive with them? Question about DC or AC coupling; • Having two power supplies implies more lines and more material budget; • How will we test the blocks. We stress the importance of thinking about how to test what we design when we design it. Also, whenever it is possible, we should include testability features; • How to cover the beam area is a hot topic. The solution with a 21 mm long chip biased on one side only seems not feasible. Power drops on the power distribution lines will be important. Also, we all agree that 3 mm are not enough to fit all the circuitry we need outside the matrix. Giovanni Anelli - CERN