ECE 412: Microcomputer Laboratory

1. ECE 412: Microcomputer Laboratory Lecture 8: CoreConnect and The PLB Bus Lecture 8

2. Outline • Bus protocol • IBM CoreConnect • PLB bus overview • PLB timing Lecture 8

3. Review Question 1 • What interfaces do the Virtex-II Pro’s PowerPC cores provide to communicate with user logic? Lecture 8

4. Review Question 1 • What interfaces do the Virtex-II Pro’s PowerPC cores provide to communicate with user logic? • PLB (Processor Local Bus) • OPB (On-Chip Peripheral Bus) • OCM (On-Chip Memory) Controller • Interrupt Controller • Device Control Register • Clock, Power Management • JTAG Port Lecture 8

5. Review Questions 2 • How does ADC work?

6. Review Questions 2 • How does ADC work? • It contains a DAC • ADC guesses an encoding d and evaluates its guess by inputting d into the DAC • Compare the generated analog output e’ from DAC with e using an analog comparator • Use a binary-search method and do this until a match is found

7. 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 1 0 1 An Example (as promised) Given an analog input signal with voltage range from 0 to 15 volts, and an 8-bit digital encoding, calculate the correct encoding for 5 volts. Then trace the binary search approach to find the correct encoding. 5/15 = d/(28-1) d= 85 Encoding as calculated: 01010101 Successive-approximation (binary search) method ½(Vmax – Vmin) = 7.5 volts Vmax = 7.5 volts. ½(5.63 + 4.69) = 5.16 volts Vmax = 5.16 volts. ½(7.5 + 0) = 3.75 volts Vmin = 3.75 volts. ½(5.16 + 4.69) = 4.93 volts Vmin = 4.93 volts. ½(7.5 + 3.75) = 5.63 volts Vmax = 5.63 volts ½(5.16 + 4.93) = 5.05 volts Vmax = 5.05 volts. ½(5.63 + 3.75) = 4.69 volts Vmin = 4.69 volts. ½(5.05 + 4.93) = 4.99 volts

8. rd'/wr Processor Memory enable addr[0-11] data[0-7] bus bus structure A simple bus Wires: • Uni-directional or bi-directional • One line may represent multiple wires Bus • Set of wires with a single function • Address bus, data bus • Or, entire collection of wires • Address, data and control • Associated protocol: rules for communication Lecture 8

9. rd'/wr Processor Memory port enable addr[0-11] data[0-7] Ports • Conducting device on periphery • Connects bus to processor or memory • Often referred to as a pin • Actual pins on periphery of IC package that plug into socket on printed-circuit board • Sometimes metallic balls instead of pins • Today, metal “pads” connecting processors and memories within single IC • Single wire or set of wires with single function • E.g., 12-wire address port bus Lecture 8

10. Timing Diagrams • Most common method for describing a communication protocol • Protocol may have subprotocols • Called bus cycle, e.g., read and write • Each may be several clock cycles • Read example • rd’/wr set low, address placed on addr for at least tsetup time before enable asserted, enable triggers memory to place data on data wires by time tread rd'/wr enable addr data tsetup tread read protocol rd'/wr enable addr data tsetup twrite write protocol Lecture 8

11. 7:0 15:8 addr data Basic protocol concepts • Actor: master initiates, servant (slave) respond • Master: device that can start transactions on the bus • Slave: device that can only respond to transactions • Direction: sender, receiver • Addresses: special kind of data • Specifies a location in memory, a peripheral, or a register within a peripheral • Time multiplexing • Share a single set of wires for multiple pieces of data • Saves wires at expense of time Time-multiplexed data transfer Master Servant Master Servant req req data(15:0) data(15:0) addr data addr data mux demux mux demux data(8) addr/data req req data addr/data data serializing address/data muxing Lecture 8

12. Master Servant Master req Servant req ack data data req 1 3 req 1 3 ack 2 4 data 2 4 data taccess 1. Master asserts req to receive data 1. Master asserts req to receive data 2. Servant puts data on bus within time taccess 2. Servant puts data on bus and asserts ack 3. Master receives data and deasserts req 3. Master receives data and deasserts req 4. Servant ready for next request 4. Servant ready for next request Strobe protocol Handshake protocol Basic protocol concepts: control methods Lecture 8

13. A strobe/handshake compromise Master Servant req wait data req 1 3 req 1 4 wait wait 2 3 data 2 4 data 5 taccess taccess 1. Master asserts req to receive data 1. Master asserts req to receive data 2. Servant puts data on buswithin time taccess 2. Servant can't put data within taccess, asserts wait ack (wait line is unused) 3. Servant puts data on bus and deasserts wait 3. Master receives data and deasserts req 4. Master receives data and deasserts req 4. Servant ready for next request 5. Servant ready for next request Fast-response case Slow-response case Lecture 8

14. Three Different Buses in CoreConnect • The PLB on-chip bus is used in highly integrated systems. It supports read and write data transfers between master and slave devices equipped with a PLB interface and connected through PLB signals. • Lower-performance peripherals are attached on the on-chip peripheral bus (OPB). A bridge is provided between the PLB and OPB to enable data transfer by PLB masters to and from OPB slaves. • The device control register (DCR) bus is used primarily for accessing status and control registers within the various PLB and OPB masters and slaves. It is meant to off-load the PLB from the lower-performance status and control read and write transfers Lecture 8

15. IBM CoreConnect Lecture 8

16. CoreConnect Main Features • CoreConnect, the IBM PowerPC® processor bus, has been licensed at no cost to more than 1500 IP developers in the past decade. • In addition, IBM provides a bridge to the I/O core solutions of IP supplier ARM. This enables ARM solutions to be used in Power Architecture-based designs. • Peripheral options include memory controllers, direct memory access (DMA) controllers, PCI interface bridges and interrupt controllers, etc. • When combined with SystemC models, available peripherals and design services, a complete PowerPC solution from system-level design to implementation can be realized. Lecture 8

17. Another View Supporting ARM I/O cores (AHB): Advanced Microcontroller Bus Architecture (AMBA) advanced high-performance bus Lecture 8

18. PLB Overview • PLB is a 64-bit bus format that supports multiple master and slave devices • Also supports 32-bit devices • Each master device is assigned a priority so that the bus can arbitrate when multiple masters want to use the bus • Slave devices are assigned one or more regions of addresses that they are responsible for handling requests • Our designs will use both the PowerPC and your logic as bus masters • PowerPC 405 supports two PLB interfaces • Instruction-side PLB for loading instructions into cache • IPLB is read-only • Data-side PLB (read-write) for data • Can tie both buses together if desired Lecture 8

19. Instruction-Side PLB • Read-only bus • Allows PowerPC to request instructions from off-chip devices • Supports four-word and eight-word transfers into instruction unit Lecture 8

20. Data-Side PLB • Supports reads and writes • One- and eight-word transfers • Uncacheable data typically one-word transfer • Can configure PowerPC to fetch multiple-word uncacheable blocks Lecture 8

21. Data-Side PLB Signals • Signaling convention: • “C405PLB” at the beginning of a signal name indicates an output from the PowerPC to the PLB • “PLBC405” at the beginning of a signal name indicates an input to the PowerPC from the PLB • Signal names are of the form [PLBC405 | C405PLB]DCU<name> • We’ll use the <name> portion of each signal to avoid wasting half of each slide on signal names Lecture 8

22. Data-Side PLB Signals • REQUEST: Indicates that the PowerPC is initiating a request over the PLB bus • RNW, ABUS[0:31], SIZE2, CACHEABLE, WRITETHRU, U0ATTR, GUARDED, CUBE[0:7] must be valid when REQUEST is asserted and remain valid until the end of the cycle when the request is acknowledged • RNW: Indicates whether the request is a read or write • Asserted = read, De-asserted = write • ABUS[0:31]: Address bus • Byte-addressed • Single-word transfers may fetch only portions of a word, controlled by the DCUBE signal Lecture 8

23. Data-Side PLB Signals • SIZE2: Specifies size of the request • Asserted = eight-word, De-asserted = one-word • CACHEABLE: Is data at this address cacheable? • Asserted = cacheable, de-asserted = un-cacheable • Un-cacheable data typically accessed using one-word requests • Can set a configuration bit in the PowerPC to request eight-word uncacheable data blocks • WRITETHRU: Indicates whether data at the address is in write-through or write-back cacheable memory • Asserted = write-through, De-asserted = write-back • Mostly used in systems with cache coherence Lecture 8

24. Data-Side PLB Signals • U0ATTR: Gives the value of the U0 (user 0) attribute bit for this address • Flag that can be set in processor register • GUARDED: Indicates whether address is in guarded storage • CUBE[0:7]: Indicates which bytes of a single-word transaction are being transferred • Restrictions exist on which combinations can be transferred • PRIORITY[0:1]: Priority of the request • Used to arbitrate between multiple bus masters • ABORT: Abort current transaction • Requirements about how PowerPC and device handle aborts at different times Lecture 8

25. Data-Side PLB Signals • WRDBUS[0:63]: Output data bus from PowerPC to PLB • ADDRACK: Indicates that PLB bus device has seen the request and latched the appropriate control signals • May be asserted as early as the same cycle as REQUEST • SIZE1: Indicates whether the device handling a request supports 32- or 64-bit transfers • Asserted = 64-bit, De-asserted = 32-bit • Valid during same cycle as ADDRACK • RDDBUS[0:63]: Data bus from PLB to PowerPC Lecture 8

26. Data-Side PLB Signals • DWDADDR[1:3]: Indicates which word of an eight-word transfer is present on the data bus • Device can return words in any order • WRDACK: Indicates that device has latched the data being written on the WRDBUS • PowerPC must hold data on the bus until acknowledged • BUSY: Indicates that the PLB bus device is processing a request • Doesn’t always prevent PowerPC from starting another request • PowerPC checks signal during SYNC operations • ERR: Device detected an error in processing request • Slave still completes request, processor decides how to handle Lecture 8

27. Timing of PLB Transactions • PLB device can acknowledge a request as early as the cycle when the request is asserted • PowerPC required to assert request and control signals continuously until device acks. • PowerPC drives write data in the same cycle as request, holds until getting write ack. • Device can return read data as early as the cycle after it acknowledges read request • PowerPC can pipeline up to two line read requests • Pipeline means to start a second request before first completes • Device is required to complete requests in order Lecture 8

28. PLB Timing: Consecutive Word Reads Lecture 8

29. PLB Timing: Pipelined Block Reads Lecture 8

30. PLB Timing: Consecutive Line Writes Lecture 8

31. Documentation • PowerPC 405 Processor Block Reference Guide • PLB IPIF v2.01a Document • Describes Xilinx’ customizable cores that interface to PLB • Platform Specification Format Reference Manual • Describes the different files used to build a SoC system • Shows you what’s going on under the hood of the GUI Lecture 8

32. Next Time • OPB bus • Using IFIP Cores to connect to the PLB and OPB busses Lecture 8