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options for clocking and serial links in the HF FEE

options for clocking and serial links in the HF FEE. Tullio Grassi 5 June 2014. HF electronics. Color code: clocks , data. ngCCM. Serial rate = fLHC x 120. SERDES mezzanine. ngFEC. ?. Recovered clock In sync with LHC. LHC Clock ( via TTC ). RM ( QIE cards).

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options for clocking and serial links in the HF FEE

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  1. options for clocking and serial links in the HF FEE TullioGrassi 5 June 2014

  2. HF electronics Color code: clocks, data ngCCM Serial rate = fLHC x 120 SERDES mezzanine ngFEC ? Recovered clock In sync with LHC LHC Clock ( via TTC ) RM (QIE cards) LHC Freq x3 (multiplier) ? RefCLK0 igloo2 SERializers RefCLK1 uHTR Pad- insertion logic Serial rate = RM_RefClk x 40 DESerializers Programmable PLL set compatibly with RM RefClk ? 125 MHz(*) fixed oscillator

  3. Design Options ngCCM SERDES mezzanine: • GBTX • igloo2 FPGA and 120.2365 MHz oscillator RM RefCLK: • make a clean clock at 3x the LHC frequency • 125 MHzfixed oscillator  see next slides

  4. ngCCM SERDES mezzanine: option with igloo2 and 120.2365 MHz oscillator Some progress porting the GBT protocol to igloo2 [http://indico.cern.ch/event/284349/] Tolerance to frequency variations of the LHC clock: ok Phase stability of the clock delivered to the FEE is not yet clear  we may need to use a separate fiber for this. Difficult to buy a rad-tol120.2365 MHz oscillator. Another option on the market is a “programmable oscillator” from cardinalxtal.com Its estimated upset cross-section in a proton environment is 4.5 E-14 cm2[https://cms-docdb.cern.ch/cgi-bin/DocDB/RetrieveFile?docid=6031&version=1&filename=SEE_on_Programmablel_Oscillator_from_Cardinal_4JUN2014.pdf].

  5. ngCCM SERDES mezzanine: option with GBX Samples of GBTX are available and are reported to be functional [http://indico.cern.ch/event/287628/session/1/contribution/12/material/slides/1.pdf] but in reality they: • are not rad-hard to tracker levels, but very likely are harder than igloo2 • need an external reference clock at the LHC frequency. Corrected GBTX chips will not need an external clock and should be available to users in Feb 2015.

  6. RM: option with fixed frequency oscillators The concept is to make readout links with a transmission capacity fixed and bigger than what we need. For the RM design we need: • Logic in the FPGA to insert “pad” words; similar logic has been used in the RCT  GCT link • Rad-tol crystal oscillators, the most likely frequency is 125 MHz. Irradiation tests on a commercial oscillator are on https://edms.cern.ch/document/1327311/1

  7. Backup

  8. Notes (*) the RM fixed oscillator can be at any frequency f : (120.2365 + margin) MHz < f ≤ 125 MHz 125 HMz oscillators are used in standard protocols and may be cheaper and faster to buy. 1) The ngCCM is allowed to transmit data asynchronously wrt LHC, this is how the existing system works in CMS. 2) The LHC period varies by 0.342 ps (worst case, heavy ion injection, see page 35 of http://indico.cern.ch/event/12273/material/slides/ , note the error ps fs). Can the igloo2 deserializer (CDR) tolerate this frequency variation ? Peak-to-peak jitter tolerance of igloo2 receiver is compatible with IEEE 802.3 [SmartFusion2 SoC and IGLOO2 FPGA Characterization Report for XAUI, Table 5] and it is at least 0.65 UI = 0.65 / 4.8 GHz = 0.13 ns  covers abundantly the LHC variations. 3) Requirements on the recovered clocks are determined by the TDC, so it is ~500ps.  to be verified, anyway it would be a “gradual” failure, not a catastrophic failure.

  9. Proposed Clocking Color code: clocks, data ngCCM Serial rate = fLHC x 120 ngFEC Recovered clock = LHC clock igloo2 SERDES Serial rate = ngCCM_RefClk x 120 LHC Clock ( via TTC ) ngCCM_RefClk 120.2365 MHz fixed oscillator RM (QIE card) uHTR Serial rate = RM_RefClk x 120 Pad- insertion logic igloo2 SERializers DESerializers RM_RefClk Programmable clock oscillator set compatibly with RM RefClk 125 MHz(*) fixed oscillator

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