Worst-Case Noise Area Prediction of On-Chip Power Distribution Network

1. Worst-Case Noise Area Prediction of On-Chip Power Distribution Network Xiang Zhang1, Jingwei Lu2, Yang Liu3andChung-Kuan Cheng1,2 1ECE Dept., University of California, San Diego, CA, USA 2 CSE Dept., University of California, San Diego , CA, USA 3 Institute of Electronic CAD, Xidian University, Xi’an, China 2014-06-01

2. Executive Summary • Problem:Previous works focus on the worst-peak droop to sign off PDN. • Worst-peak noise ≠ Worst timing (delay) • Our goal: To predict a PDN noise for better timing sign off. • Observation: The noise area of PDN => Behavior of circuit delay • Case study: Design the worst-case PDN noise area • Provide analytical solution for a lumped PDN model • Design an algorithm for general PDN cases • Results: Worst-area noise introduces 1.8% additional propagation delay compared to worst-peak noise from our empirical validation under a complete PDN path.

3. Power Distribution Network (PDN) • Power supply noise • Resistive IR drop • Inductive Ldi/dtnoise • PDN model

4. Motivation • Performance sensitivity on PDN voltage drop • Increased signal delay [Saint-Laurent’04] [Jiang’99] • Clock jitter [Pialis’03] Delay vs supply voltage(courtesy of [Saint-Laurent’04])

5. PDN Noise Area vs Delay • Delay is measured under a modified C432 of ISCAS85 circuit in 130nm node

6. Problem Formulation • PDN Characterization • Impulse Response h(t) • Voltage Noise: • Input to PDN system • Transient load current demand i(t) • Assumption: • All on-die loads lumped into a single load • Total current is bounded

7. Problem Formulation • Worst-case peak noise [Hu et al @ SLIP2009] • where the worst-current : • Voltage Noise Area • Integral within sliding window • Window size T corresponds to one clock cycle • Defined as , a function of input current • Worst-case optimization • Design of current and voltage drop • Achieve maximum noise area Aw and interval • Can be solved by polynomial-time method when when

8. Problem Simplification • Binary-valued worst current • Can be proved that only switches between 0 and 1 • Current decomposition • equals the superposition ofa series of step inputs • Single step input & response • Step response • Integrate into ramp response • Noise area function

9. Simplified Problem Formulation • A linear-constrained linear optimization problem • Input • A power network system with impulse response h(t) • Given window size T • Output • Window location • Phase delay of step inputs, • Objective • Maximum noise area Aw within • Constraints • , t is

10. Case Study: RLC Tank Model • Impedance Profile: , where • Assume Q>0.5, system is underdamped • Step Response : • where • Ramp Response : • where

11. Worst Noise Area Prediction for RLC Tank • Given a window size T, worst-area noise is • is set to a relatively large value when . • is • is the time when local peaks/valleys of occur. • Solved by setting since is piecewise-defined func. • Case 1 (): is the solution of , i.e. • Case 2 (): where .

12. Case Study: Worst Noise Area Prediction for General PDN Cases • Real PDN structure is complicated • Consists of multiple frequency components • Develop algorithm • Algorithm design for general cases • Given window size T and arbitrary impulse response • Determine the phase delay of each step input • Constructs by superposing • Maximum noise is achieved

13. Intuition • Align all together to generate • Select one point from to determine the phase delay • Maximize (+) by choosing peak points • Minimize (-) by choosing valley points • Determine as the last peak of . • = sum of all peaks- sum of all valleys

14. Algorithm Design • Given & • Impulse response and window size • Generate , and • Step responses and its transformation • Extract all peaks and valleys of • Linear scanning on • Calculate each peak-to-valley distance • Determine phase delay accordingly • Determine (t) by and its sign (±) • Construct • adding up all together

15. Complexity Analysis • Our algorithm consists of finite operations • Step response transformation • Linear scan for peaks & valleys extraction • Worst-case current construction • Overall complexity is O(n) • Finite amount of operations • Each operation consumes no larger than linear runtime

16. Experimental Design and Results • Setup: • Matlab R2013a • HSPICE D-2013.03-SP1 • Cadence Allegro Sigrity Power SI 16.6 • Ansoft Q3D 12.0 • ISCAS85 circuit under 0.13um cell lib • Intel i7 Qual-Core 3.4GHz w/16GB PCDDR3 • PDNtest cases • Single RLC tank • Cascaded RLC tanks • A complete PDN path extracted from industrial design

17. Worst-Peak and Worst-Area Noise of a Single RLC Tank Case Nominal Vdd= 1V, T=17ns Both load current activities stop at

18. Worst-Area and Worst-Peak Noise of Multi-Stage Cascaded RLC Tanks • Circuit Model • Three Cases Case I can be approximated to three single RLC tanks:

19. Worst-Area and Worst-Peak Noises of Multi-Stage Cascaded RLC Tanks • Compare the worst-case noise predcition from the analytical solution approximations from RLC tank decomposition vs solution of Algorithm 1 • for • Prediction Error(on average) : • 7.75% for the worst-peak noise • 12.3% for the worst-area noise

20. Worst-Peak and Worst-Area Noise of a Complete PDN Path • Impedance Profile:

21. Worst-Peak and Worst-Area Noise of a Complete PDN Path • Worst-peak and worst-area noise solved by Alg. 1 • ,

22. Delay Measurement of a Complete PDN Path • Send input pulse every 100ps and record delay of the datapath at the output port of C432 (ISCAS85) case • Compare the delay under worst-peak and worst-area noise • Results:

23. Conclusions • Problem:Previous works focus on the worst-peak droop to sign off PDN. • Worst-peak noise ≠ Worst timing (delay) • Our goal: To predict a PDN noise for better timing sign off. • Observation: The noise area of PDN => Behavior of circuit delay • Case study: Design the worst-case PDN noise area • Provide analytical solution for a lumped PDN model • Design an algorithm for general PDN cases • Results: Worst-area noise introduces 1.8% additional propagation delay compared to worst-peak noise from our empirical validation under a complete PDN path.

24. Q & A Thank You!

25. Backup Slides

26. Delay Measurement of Single RLC Tank Case • Send input pulse every 100ps and record delay of the datapath at the output port of C432 (ISCAS85) case