EE222_Lecture 5 On-Chip Power Distribution Network January 23, 2018

1. EE222_Lecture 5 On-Chip Power Distribution Network January 23, 2018 Reference: Prof. E. G. Friedman, Univ. of Rochester

2. High voltage Low voltage 10 metal layers Line width – 150 m to 15 km Interlayer spacing – 200 m to 1000 m US Power Distribution System IC Power Distribution Grid National vs Chip Level Power Grids Area – 9,629,091 km2 Area – 6.45 cm2 (1 in2) Scale factor 1.5 x 108 10 metal layers Line width – 1 μm to 100 μm Interlayer spacing – 2 μm to 10 μm

3. IC Power Distribution System Iload Vdd Voltageregulator Integrated circuit Board Package Regional Power Distribution System Macro vs Micro Power Delivery • Four level of hierarchy • Voltage scaled to lower losses • Simple interconnect structure • Long distance power delivery • Four level of hierarchy • Dimensions scaled to lower losses • Sophisticated interconnect structure • Short distance power delivery

4. On-Chip Power Distribution Networks in High Speed Integrated Circuits Agenda • Motivation • On-chip power distribution networks • Computer-aided design and analysis • Electrical characteristics of single layer grids • Scaling of on-chip power supply voltage drop • Impedance characteristics of multi-layer grids • Summary

5. On-Chip Power Distribution Networks in High Speed Integrated Circuits Agenda • Motivation • On-chip power distribution networks • Computer-aided design and analysis • Electrical characteristics of single layer grids • Scaling of on-chip power supply voltage drop • Impedance characteristics of multi-layer grids • Summary

6. Problem of Power Delivery Objective: Deliver power to the load while maintaining the power supply voltages within target noise margins under specified load demands Obstacles: Power lines are not ideal and have finite resistance and inductance • Resistive noise VR = IR • Caused by high transient currents drawn by the load • Inductive noise VL = L di/dt • Caused by high current slew rates di/dt produced by the load

7. Moore's Law—Integrated Circuit Complexity Rapidly Increases

8. Clock Frequency Increases with Scaling

9. Power Consumption Increaseswith Rising Complexity and Speed

10. Power Current Increases Drastically with Technology Scaling

11. ITRS Forecast for Power Current Demands • Rate of increase in transient current is approximately double the increase in average current • Due to the increase in clock frequency • Agrees with ideal scaling analysis (S is the scaling factor) • Average current per circuit area IA scales as S • Transient current per circuit area dIA/dt scales as S2

12. Projections of Transient Current Demands in ICs • Current slew rate demands are rising faster than average current demands • Inductive noise is increasing faster than resistive noise

13. Resource Requirements for On-Chip Power Distribution Networks • Average current and transient current demands of integrated circuits increase with technology scaling • Power distribution networks use an increasingly larger share of on-chip resources to satisfy increasing demand • Share of metal resources increases • IBM Power4 CPU: 28% of on-chip metal • Hewlett-Packard PA-8500: >35% of on-chip metal • On-chip decoupling capacitors occupy significant area • Typically 5% to 15% of chip area Optimizing the on-chip power distribution network can significantly increase the share of metal resources available for signal routing

14. Inductive Characteristics of Power Distribution Networks • Affects the integrity of the signals • Primary current return path in on-chip single ended signals • Return current flows through neighboring signal wires • Causes signal-to-signal crosstalk • Affects the integrity of the power supply • Simultaneous switching noise • RLC resonances within the power grid

15. Design of Power Distribution Grid Impedance Characteristics • Inductive characteristics of power distribution grids affect • Efficient placement of decoupling capacitors • Model of simultaneous switching noise • [Vemuru, TAP’96], [Tang and Friedman, TVLSI’02] • RLC analysis and verification of on-chip power distribution networks • [Nassif and Kozhaya, ISCAS’00], [Bobba and Hajj, ISLPED’01], [Zheng and Tenhunen, TAP’01] • Analysis of resonant behavior in on-chip power grids

16. Behavioral Pre-floorplan analysis (uniform current distribution is assumed) basic track topology, line width, pitch andlayer allocation, I/O pad number, and location RTL Logic Floorplan-based analysis (uniform current distribution within blocks) block-specific line width and pitch Circuit Layout Post-layout back annotation and analysis (based on worst case current waveforms)minor local adjustments of the grid Design Flow of Global Power Distribution Networks VLSI Design Flow Power Grid Design Flow Resourceallocation Power gridtradeoff data Global power distribution networks are conservatively designed to satisfy worst case requirements

17. On-Chip Power Distribution Networks in High Speed Integrated Circuits Agenda • Motivation • On-chip power distribution networks • Computer-aided design and analysis • Electrical characteristics of single layer grids • Scaling of on-chip power supply voltage drop • Impedance characteristics of multi-layer grids • Summary

18. Physical Characteristics of P/G Networks

19. On-Chip Power Distribution Networks • Design of on-chip power distribution networks is constrained by several considerations • Network impedance • Metal resources • Electromigration constraints • Structure of on-chip power distribution network is often combination of several basic styles • Routed • Mesh • Grid • Planes

20. Routed Power Distribution Networks • Routed networks are typically used in low power circuits with limited interconnect resources • Low area overhead • Relatively low robustness • Failure of single interconnect segment usually leads to circuit failure

21. Mesh Power Distribution Networks • Mesh networks are typically used in relatively low power circuits with limited interconnect resources • Greater area overhead • Improved robustness

22. Mesh Power Distribution Networks 3-D Mesh networks are typically used in relatively low power circuits with limited interconnect resources Greater area overhead Improved robustness

23. Grid Power Distribution Networks • Grid networks are the preferred style in contemporary high power, high complexity circuits • High area overhead • Highly robust

24. Power and ground planes Power Distribution Planes • Power planes are used in high speed circuits where signal integrity is primary concern • Greatest area overhead • Superior impedance characteristics

25. Cascaded Power/Ground Rings For ICs where pads are located along periphery Primary advantage: Signal routing at higher metal layers is possible

26. Power Distribution Planes Power planes are used in high speed circuits where signal integrity is primary concern Greatest area overhead Superior impedance characteristics

27. Evolution of On-Chip Power DistributionNetworks in Alpha Microprocessors Alpha 2126465 W, 39 A0.18 mm, 7Mflip-chip Alpha 2116450 W, 16 A0.5 mm, 4M Alpha 2126472 W, 33 A0.35 mm, 6M Alpha 2106430 W, 9 A0.75 mm, 3M Single layer grid Two layer grid Power planesnot requiredfor power deliverybut retained for data signal integrity Two powerplanes Gronowski et al., High-Performance Microprocessor Design, JSSC, Vol. 33, No. 5, pp. 676-686, May 1998.

28. Summary: Power Distribution Systems • Electrical behavior of a power distribution system is systematically described • Controlling the resistance of the decoupling capacitors and interconnect is essential for efficient design of low impedance power distribution systems • Maintaining adequate damping characteristics of chip-package resonance is particularly challenging • On-chip capacitors should have a relatively high effective resistance • Two-dimensional nature of package and on-chip networks • This treatment provides basis for efficient management of resonant behavior in complex package and on-chip networks

29. Motivation On-chip power distribution networks Computer-aided design and analysis Electrical characteristics of single layer grids Scaling of on-chip power supply voltage drop Impedance characteristics of multi-layer grids Summary On-Chip Power Distribution Networks in High Speed Integrated Circuits Agenda

30. Behavioral Pre-floorplan analysis (uniform current distribution is assumed) basic track topology, line width, pitch andlayer allocation, I/O pad number, and location RTL Logic Floorplan-based analysis (uniform current distribution within blocks) block-specific line width and pitch Circuit Layout Post-layout back annotation and analysis (based on worst case current waveforms)minor local adjustments of the grid Design Flow of Global Power Distribution Networks VLSI Design Flow Power Grid Design Flow Resourceallocation Power gridtradeoff data Global power distribution networks are conservatively designed to satisfy worst case requirements

31. Pre-floorplan Stage Grid topology Location of power/ground pads Width and pitch of power/ground metal layers Ad hoc assumptions to estimate on-chip current Information obtained from previous circuits is scaled

32. Post-Floorplan Stage Important intermediate stage Majority of problems are detected and mitigated in this step Widen existing power lines Insert additional lines Increase on-chip decoupling capacitance Moderate complexity permits iterative analysis More accurate current estimation is achieved at this stage

33. Current Estimation

34. Post-Layout Stage Final stage, physical design is close to completion Major modification to power network is extremely difficult Only minor changes can be tolerated Reason for overly conservative design at pre- and post-floorplan stages

35. Nonlinear simulation • Linear simulation Power Distribution Analysis • Global problem, current at one location can affect voltage at all other locations • Entire power grid must be analyzed simultaneously • If partitioned, can produce serious error • Number of nodes in grid >> 25 million in large microprocessor • Must also consider transistor currents • Requires SPICE-like accuracy - infeasible • Devices – assume constant VDD and GND – Partitioned into blocks and simulated in parallel • Iterate with more accurate VDD and GND - May not converge • Interconnect – RLC of power grid and transistor currents  time varying current sources • Linear simulator across entire power distribution network • (Voltage at all power grid tap points) • Constant VDD and GND for transistors are primary problem to approach • Conservative since overestimated currents

36. Typical 2-D Power Network Model

37. Static Analysis Characterize long term average IR drop along network Based on average steady state current drawn from power supply Capacitances are assumed as open circuit Inductances are assumed as short circuit Complexity significantly lower than dynamic analysis Identifies weak spots Dynamic analysis is performed on weak spots Also useful to characterize electromigration reliability

38. Dynamic Analysis Type of transient analysis Can observe temporal variation of power supply noise Capacitance and inductance need to be considered Time correlation of various circuit blocks can also be examined Complexity is significantly higher

39. On-Chip Power Distribution Networks in High Speed Integrated Circuits Agenda • Motivation • On-chip power distribution networks • Computer-aided design and analysis • Electrical characteristics of single layer grids • Grid types and general inductive properties • Inductance variation on grid dimensions • Inductance variation with frequency • Inductance/resistance/area tradeoffs • Scaling of on-chip power supply voltage drop • Impedance characteristics of multi-layer grids • Summary

40. General Power Transmission Circuit • Equivalent inductance diagram • Forward inductance Lpp • Return inductance Lgg • Mutual inductive coupling Lpg

41. Inductance of Power Current Loop I I Lloop = Lpp + Lgg – 2Lpg • How to minimize loop inductance Lloop ? • Minimize partial self inductance, Lpp and Lgg • Maximize the partial inductance Lpg • The mutual coupling

42. I1 I2 How to Minimize Lpp and Lgg ? • In general, the forward current and return current paths consist of several conductors in parallel • Consider two parallel conductors • Net inductance of a parallel circuit • How to minimize the net parallel inductanceL1||2 ? • Minimize partial self inductance,L11andL22 • Minimize the coupling • Partial mutual inductanceL12

43. Antiparallel currents I1 I2 Parallel currents I1 I2 Parallel versus Antiparallel Currents • Strong coupling of antiparallelcurrents reduces the circuit inductance • Strong coupling of parallelcurrents increases the circuit inductance • Line separation determines the line coupling (per length) • To minimize circuit inductance • Parallel currents should be spatially separated from each other • Antiparallel currents should be placed in close proximity

44. Three Power Grid Types Investigated • Non-interdigitated • The power lines occupy one half of the grid, the ground lines occupy the other half • Interdigitated • Power and ground lines are interdigitated and uniformly distributed • Paired • Power and ground lines are placed in uniformly distributed power/ground line pairs

45. P Average width of the current loop Cross Sectionof Non-interdigitated Grid • This configuration has a relatively high inductance • Coupling of parallel currents is relatively strong • Separation between parallel currents is equal to the line pitch P • Coupling of antiparallel currents is relatively weak • Separation between antiparallel currents is large • Intuitively, equivalent to the width of the current loop • On average, half of the grid width • How can this grid be improved to lower inductance? • Interdigitate power and ground lines • Spread lines over the entire width of the grid

46. P 2P Effective width of the current loop Cross Section of Interdigitated Grid • Lower inductance as compared to non-interdigitated grids • Coupling of parallel currents is relatively weak • Separation between parallel currents is equal to 2P • Stronger coupling of antiparallel currents • Separation between antiparallel currents is equal to P • Smaller effective width (and area) of the current loop • Can grid be further improved to lower inductance? • Place the power and ground lines in close proximity to minimize the effective width of the current loop

47. 2P Effective width of the current loop Cross Section of Paired Grid • Lower inductance as compared to interdigitated grids • Coupling of parallel currents is relatively weak • Separation between parallel currents is equal to2P • Strong coupling of antiparallel currents • Separation between antiparallel currents is the minimum spacing S0 • Small effective width (and area) of the current loop S0 • No further significant improvements?

48. Analysis Tools and Assumptions • FastHenry* is used to evaluate the grid inductance • Magneto-quasistatic approximation • Displacement currents through interconnect capacitances are ignored • Accurate for power and ground lines • Geometric and technology parameters • Metal lines are 1 mm thick • Metal resistivity is 1.72 mW·cm • Within the resistance range reported for Cu interconnect • Grid length is 1000 mm • Minimum line width and spacing are 0.5 mm * M. Kamon, M. J. Tsuk, and J. White, "FastHenry: A Multipole-Accelerated 3-D Inductance Extraction Program,"IEEE Transactions on Microwave Theory and Techniques, Vol. 42, No. 9, pp. 1750-1758, September 1994

49. On-Chip Power Distribution Networks in High Speed Integrated Circuits Agenda • Motivation • On-chip power distribution networks • Computer-aided design and analysis • Electrical characteristics of single layer grids • Grid types and general inductive properties • Inductance variation on grid dimensions • Inductance variation with frequency • Inductance/resistance/area tradeoffs • Scaling of on-chip power supply voltage drop • Impedance characteristics of multi-layer grids • Summary

50. Frequency = 1 GHz Non-interdigitated grid, 1 mm  1 mm lines Interdigitated grid, 1 mm  1 mm lines Paired grid, 1 mm  1 mm lines Dependence of Inductance on Grid Type • Grid inductance depends on grid type • Non-interdigitated grids have the largest inductance • Interdigitated grids have intermediate inductance • Paired grids have the lowest inductance