1 / 19

Department of Computer Science and Software Engineering University of Wisconsin-Platteville

Computer Architecture and Operating Systems CS 3230: Operating System Section Lecture OS-8 Memory Management (2). Department of Computer Science and Software Engineering University of Wisconsin-Platteville. Outlines. Paging Address Translation Page Table Page Table Structure

chiko
Download Presentation

Department of Computer Science and Software Engineering University of Wisconsin-Platteville

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Computer Architecture and Operating SystemsCS 3230: Operating System SectionLecture OS-8Memory Management (2) Department of Computer Science and Software Engineering University of Wisconsin-Platteville

  2. Outlines Paging Address Translation Page Table Page Table Structure Shared Pages

  3. Paging Each process is divided into a number of small, fixed-size partitions called pages Physical memory is divided into a large number of small, fixed-size partitions called frames Page size = frame size Usually 512 bytes to 16K bytes ,lately tends to be 4K To run a program of size n pages, need to find n free frames and load program

  4. Page Table Page Table : per process data structure that provides mapping from page to frame Logical address space: continuous Physical address space: fragmented

  5. Page Table: Protection Process may not use the whole page table Unused portions of the page table are protected by valid/invalid bit Try to address these pages will result in a trap with “memory protection violation” Problem: size of page table Solution: Page-Table Length Register (PRLR)indicates size of the page table (discussed later)

  6. Paging: Address Translation Logical address (Address generated by CPU) consists of page number and offset from beginning of the page Physical address consists of frame base address and offset from beginning of the frame Address Translation Architecture:

  7. Page Table: Implementation Page table is kept in main memory. Problem: each page table must fit in one frame /page Page-Table Base Register (PTBR) points to the page table (physical address of the page table) Page-Table Length Register (PRLR) indicates size of the page table (# of current valid pages in the table) Problem: every data/instruction access requires two memory accesses One for the page table and one for the data/instruction Solution: fast-lookup hardware cache called associative memory or Translation Look-aside Buffer (TLB) What happens on context switch? clear TLB (destroying all info they hold)

  8. TLB On page access: page # is first looked in TLB if found (cache hit) can immediately access page if not found (cache miss) have to look up the frame in the page table

  9. Paging: Effective Access Time Associative TLB Lookup =  time unit Assume memory cycle time is 1 microsecond Hit ratio – percentage of times that a page number is found in the TLB Hit ratio =  Effective Access Time (EAT): EAT = (1 + )  + (2 + )(1 – ) = 2 +  – 

  10. Page Table Structure Problem: Address space of modern computer system is 232 to 264 Each page table must fit in one frame /page However , size of page table is potentially large As a result , page table searching time is potentially large Solution: Hierarchical Paging Hashed Page Tables Inverted Page Tables

  11. Page Table Structure Hierarchical Paging Hashed Page Tables Inverted Page Tables

  12. Hierarchical Page Tables Break up the logical address space into multiple page tables A simple technique is a two-level page table

  13. Hierarchical Page Tables A logical address (on 32-bit machine with 4K page size) is divided into: a page number consisting of 20 bits a page offset consisting of 12 bits Since the page table is paged, the page number is further divided into: a 10-bit page number a 10-bit page offset Thus, a logical address is as follows:

  14. Hierarchical Page Tables

  15. Hashed Page Tables Used with address spaces > 32 bits and < 64 Hashes logical page number. In case of hash collision, page references are linked structure

  16. Inverted Page Table Used with address spaces > 64 bits Only one (global) page table for all processes One entry for each frame Need information about the process that owns that page Search table to find the frame that logical page refers to Use hash table to decrease the searching time

  17. Inverted Page Table

  18. Shared Pages Paging helps code reusing One copy of read-only (reentrant) code shared among processes (i.e., text editors, compilers, window systems) Shared code must appear in same location in the logical address space of all processes

  19. Segmentation with Paging Problems of external fragmentation and lengthy search times can be solved by paging the segments

More Related