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Straw electronics status. Covers. Pre-production 15 boards of each type delivered Vito has tested 6 of each type 6 boards did not pass 1 minor problem with parameters set too tight 0.65A current instead of 0.64A The rest has problems with DAC programming Only read back, writing OK
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Covers • Pre-production • 15 boards of each type delivered • Vito has tested 6 of each type • 6boards did not pass • 1 minor problem with parameters set too tight • 0.65A current instead of 0.64A • The resthas problems with DAC programming • Only read back, writing OK • Firmware checked, timing very tight for read-back • With new firmware (version 9) all boards are OK, yield 100% • The hole for HV connector too tight, 9.8 mm instead of 10mm • Should be fixed for full production • Testing finished • Full production (confusion) • December 2013/Jan 2014
Patch panels • HV • Fully passive now • No DCS • If problem, stop experiment and manual intervention • Modularity changed • 32 channels/chamber to better isolate the problem • 8 channels/view • 4 channels/PP • 2 high precision modules with 16 outputs each • No interlock (?) • Fischer connector with pull lock • Gender • Male on the PP • Female on cable for safety • New product with this arrangement • production 10 weeks • Provisional PP for testing till having final connectors • Equip only 1 input with SHV
Patch panels • LV • The connector on LV module is now only D-SUB 37pin (low current) • 2inputs 8V/10A sufficient in terms of current • Final cover consumption ~0.7A/cover • Save on 2 LV modules/chamber • Possibility to improve current measurement • Special chip for measuring current on ‘high’ side • Both PP should go to the production as soon as we know for sure • Type of the connectors • Cable types • Mechanical constraints – mounting, (dis-)assembly, etc • Simple objects – production fast
Cables • Ethernet/data cables • Need to define the length • How many different? • Wait for the 1st chamber installed and measure the legth • February 2014 • HV • HV now standard 5kV coax • SHV on crate side, Fischer on PP side • No interlock • Production at CERN • LV • Harness needed from D-SUB connector • Cable cross-section to PP smaller, ~4mm2 for ~1V drop • Shield?
SRB • The first FPGAs received • Model with 2 core CPU in December • Definition of components, protocols • “CPU or not CPU” for data to pc-farm • Firmware more performant but also more difficult to write, change, maintain • C-code easier to write, debug, change • Prototype January?