Our goal

1. VLSI Design Spring03 UCSCBy Prof Scott Wakefield Final ProjectBy Shaoming Ding ding@soe.ucsc.eduJun Hu hujun@soe.ucsc.edu

2. Our goal • The goal of the project is to design a high speed 3-tap Finite Impulse Response (FIR) filter using explicit arithmetic units instead of high level behavioral operations to speed-up the computation. The arithmetic units include a 48-bit adder and a 24-bit multiplier.

3. The structure of the FIR • Usual Implementation • Project Implementation

4. Multiplier • Standard multiplication

5. Multiplier • Booth’s algorithm (Radix-2)

6. ai ai-1 Recoded ai 0 0 0 0 1 +1 1 0 -1 1 1 0 Multiplier • If Booth's recoded is +1 , then set else if Booth's recoded is -1, then else 23 22 21 20 … 4 3 2 1 0 (0)

7. The implementation of multiplier in the project • Radix-4 Booth 23 22 21 19 … 9 8 7 5 4 3 1 0 (0)

8. The implementation of multiplier in the project • The Structure

9. Carry Save Adder (CSA) • Basic idea The basic idea is that three numbers can be reduced to 2, in a 3:2 compressor, by doing the addition while keeping the carries and the sum separate. A 10111001 B 00101010 Carry In 00111001 Sum 10101010 //Sum and Carry comes out from CSA Carry Out 00111001 Result 100011100 //This uses propagate adder

10. Carry Save Adder (CSA) • Wallace carry save adder tree • Full 3:2 compressor on k-bit-word.

11. 48-bit Carry Look-ahead Adder

12. 48-bit Carry Look-ahead Adder XOR XOR

13. Final Results

14. Summary • The advantage of our structure • Concurrent computation of each tap instead of the sequential one. • Multiplier concurrent computation of partial products and summation using Wallace Tree via Carry-save Adder. • Carry Look-ahead Adder in the final addition. • Conclusion • Using arithmetic units (a 48-bit adder and a 24-bit multiplier.) instead of high level behavioral operations can highly speed-up the computation