Our Goal (again)

1. Our Goal (again) • Discuss significant industry trends/events • Build significant functions w/ basic circuits • Understand high-level language translation • Know how a program runs in hardware • Write more hardware-aware programs

2. Microarchitecture • Microarchitecture begins to answer:“How does hardware understand software?” • Every microarchitecture design is constrained by hardware beneath and software above • It addresses how physical design meets instruction design

3. Physical Design • How do all the pieces communicate? • Buses • How does each piece know what to do? • Control signals • What are all the pieces? • Know your registers • Others: ALU, memory, I/O devices • The master piece: control unit

4. The IJVM Microarchitecture

5. Why the IJVM? • IJVM = Integer Java Virtual Machine • Why study this machine? • Simple (relative to most modern CPUs) • Universal (many similarities to modern CPUs) • The “Integer” implies no floating point • Try an instruction: CPP = LV + TOS • Basic sequence: B bus, ALU, C bus

6. Of Clocks and Timing • Clock pulse frequency isn’t whole story • Each pulse sub-divided into sub-cycles • Not necessarily pipelined • Sub-cycles • Set up control signals (at control store) • Load up B bus from exactly one register • Run ALU, shifter • Propagate C bus data to one or more registers • Establish values for registers (at rising edge of pulse)

7. Timing Diagram

8. The Mic-1

9. Some Questions • Why does the ALU and shifter have a time delay? How much time delay is it? • What is the ALU doing while the control signals are being set up? • What about the gap after C bus propagation? Is it good or bad? How can we get rid of it?

10. Microinstructions • Microinstruction not same as instruction • Contains all the control signals • So far, we need 29 of them • 9 for C bus enabling • 9 for B bus enabling • 8 for ALU, shifter control • 3 for read/write/fetch control

11. IJVM Microinstruction

12. Microinstruction Practice • SP = SP + 1 • TOS = CPP + LV + OPC • TOS = PC = CPP + 1 • TOS = CPP / 2 • H = 128 • Hint: use the shifter operations

13. Memory Operations • For data read/write: MAR, MDR • One for actual data and one for address • Both are 32-bit (MDR has 4 bytes of data) • MAR has address of first of 4 bytes • For fetching instructions: PC, MBR • PC is for 32-bit addresses • MBR is for an 8-bit instruction • MBR receives the byte addressed by PC • B bus prepends 0s or sign to MBR for 32 bits

14. MAR Mapping

15. Reads and Writes • Read • MAR to RAM address • RAM data (32 bits, word boundary) to MDR • PC, MBR disabled • Write • MAR to RAM address • MDR to RAM data (32 bits, word boundary) • PC, MBR disabled

16. Fetches • PC to RAM address • RAM data (8 bits, byte boundary) to MBR • MAR, MDR disabled

17. Beware of Read Delay • A common program assignment: Z = X + Y • This translates to • Read X into R1 (RAM read) • Read Y into R2 (RAM read) • Add R1 and R2 • Store sum in Z (RAM write) • Problem comes in at Add statement • R2 is not ready!

18. Building in Delays • Solution is to plan a delay • Need to delay one clock cycle • Most CPUs need much longer delays • Read initiated at end of clock cycle 1 • Do something else at clock cycle 2 • Use result of read at clock cycle 3 (or later)

19. if (CPP == LV) TOS = 1 else OPC = LV PC = PC + 1 H = LV (ADDR=76) CPP - H (ADDR=80 and JAMZ = 1) PC = PC + 1 80 OPC = LV (ADDR=77) 180 TOS = 1 (ADDR=77) Ordering Microinstructions

20. Choosing Next Microinstruction • N, Z bits set for negative, zero results • JAMN, JAMZ bits initiate tests for N, Z • Together, a branch is established • Use ADDR alone unless… • (JAMN and N) or (JAMZ and Z) = 1 • ADDR modified if a JAM test succeeds • MPC can also be loaded from MBR