2006 ITRS Public Conference Emerging Research Devices Hsinchu, Taiwan Ambassador Hotel

1. 2006 ITRS Public Conference Emerging Research Devices Hsinchu, Taiwan Ambassador Hotel December 5, 2006 Jim Hutchby – SRC

2. ITRS Emerging Research Devices Working Group • Mike Garner Intel • Makoto Yoshimi SOITEC • Kristin De Meyer IMEC • Tak Ning IBM • Philip Wong Stanford U. • Luan Tran Micron • Victor Zhirnov SRC • Simon Deleonibus LETI • Thomas Skotnicki ST Me • Yuegang Zhang Intel • Kentaro Shibahara Hiroshima U. • Philippe Coronel ST Me • Phil Kuekes HP • Christian Gamrat CEA • Dan Herr SRC • Dave Roberts Air Products • Ken Uchida Toshiba • Shin-ichi Takagi U. Tokyo • Yasuo Wada Waseda U. • Hiroyugi Akinaga AIST • Matsuo Hidaka ISTEK • Satoshi Sugahara Tokyo Tech • Tetsuya Asai Hokkaido U. • Wei-Xin Ni NDL • George Bourianoff Intel/SRC • Joe Brewer U. Florida • Toshiro Hiramoto U. Tokyo • Jim Hutchby SRC • Mike Forshaw UC London • Rainer Waser RWTH A • In Yoo Samsung • Lothar Risch Infineon • Peter Zeitzoff Freescale • Murali Ramachandran Freescale • Erik DeBenedictis SNL • Lou Lome IDA • U-In Chung Samsung • In-Seok Yeo Samsung • Ralph Cavin SRC • Zoran Krivokapic AMD • Hiroshi Mizuta Tokyo Tech • Seiichiro Kawamura Selete • Hiroshi Kotaki Sharp • Yuji Awano Fujitsu • Kojiro Yagami Sony • Shigenori Hayashi Matsushita • Yasuo Inoue Renesas Tech • Fumiyuki Nihei NEC

3. New Materials Model Knowledge 0 1 Scope of Emerging Research Devices2006/7 New Memory and Logic Technologies New Architecture Technologies Nanotubes Molecular devices Spin states Emerging Information Processing Concepts

4. Create a New Chapter in 2007 Emerging Research DevicesOrganization & Component Tasks (2007) Emerging Research Devices Emerging Materials Emerging Logic and Memory Devices Emerging Architectures

5. 2006 ERD/ERM WorkshopsCo-sponsored by NSF

6. Required characteristics: Scalability Performance Energy efficiency Gain Operational reliability Room temp. operation Preferred approach: CMOS process compatibility CMOS architectural compatibility What are we looking for? Alternative state variables (Beyond Charge State) • Spin state • Molecular state • Strongly correlated electron state • Atomic quantum state • Electric dipole orientation • Magnetic flux quanta • Mechanical deformation • Photon (intensity, phase, ..) Alternative state variables • Spin–electron, nuclear, photon • Phase • Quantum state • Magnetic flux quanta • Mechanical deformation • Dipole orientation • Molecular state

7. Transfer to PIDS 2005 ITRS ERD: Table 57 Emerging Research Memory Devices Demonstrated and Projected Parameters

8. > 20 >16 - 18 >18 - 20 < 16 For each Technology Entry (e.g. 1D Structures, sum horizontally over the 8 Criteria Max Sum = 24 Min Sum = 8 Critical EvaluationMemory

9. Table 57a: Capacitance-based memory technologies

10. Table 57b: Resistance-based memory technologies

11. Example – CNT cross-bar memory Rueckes T. et al., SCIENCE 289 (5476): 94-97 JUL 7 2000 Moving Atoms Concept • Each memory element is based on suspended crossed carbon nanotubes. • Cross-bar array of CNT forms mechanically bi-stable, electrostatically-switchable device elements at each cross point. • The memory state is read out as the junction resistance. Expectations: n=1012 bits/cm2, f=100 GHz

12. Numerical data will be updated We will have two tables for Emerging Research Memory Technology Entries: Capacitance-based memory technologies Resistance-based technologies. Put nanomechanical memory into the new tables Transfer Nanofloating Gate Entry to PIDS/Transition Table. Memory Technologies for 2007 new ERD Chapter

13. Sub- Categorize Molecular and Spin 2005 ITRS ERD: Table 59 Emerging Research Logic Devices Demonstrated and Projected Parameters

14. Spin Domain wall manipulation Ferromagnetic phase change (nano-domains) Spin transport modulation Spin torque transfer Individual and or collective spin manipulation Molecular devices Crossbar coupling elements Molecular logic elements and interconnects Intra molecular logic elements Sub-categories for Spin and molecular devices

15. > 20 >16 - 18 >18 - 20 < 16 For each Technology Entry (e.g. 1D Structures, sum horizontally over the 8 Criteria Max Sum = 24 Min Sum = 8 Critical EvaluationLogic

16. Conclusions from ERD Logic Devices Workshop(September 21, 2006) Logic device conclusions • Continued analysis of alternative technology entries likely will continue to yield the same result: • Nothing beats MOSFETs overall for performing Boolean logic operations at comparable risk levels • Certain functions, e.g. image recognition (associative processing), may be more efficiently done in networks of non-linear devices rather than Boolean logic gates • “Plasticity” of nonlinearity may be potentially useful

18. Basis of Existing Assessments of Logic Devices A possible ultimate evolution of on-chip architectures is Asynchronous Heterogeneous Multi-Core with Hierarchical Processors Organization MF(n) – application-specific processor implementing a specific macro-function (may need specialized devices) General Purpose Processor MF1 MF2 MF3 MF4 General Purpose Processor MF12 MF5 MF11 MF6 MF10 MF9 MF8 MF7 Supplementing CMOS

19. Consider new logic technologies that supplement CMOS to provide enhanced hardware capability and can be optimally executed with alternative devices Determine appropriate metric and compare to Si on the specialized application Determine if proposed application contains a standard set of “macro-functions” Understand the performance of the device in terms of its non-linear characteristics Think in terms of heterogeneous co-processors integrated with traditional CPU Proposed new focus of Logic Section

20. Image recognition Speech recognition DSP (cross correlation) Data Mining Optimization Physical simulation Sensory data processing (biological, physical) Image creation Cryptographic analysis Potential supplemental applications

21. Preparing for the 2007 re-write of the ERD Chapter. Conducted four workshops in 2006 on Emerging Research Memory, Logic, Architectures and Materials (co-sponsored by ITRS and NSF) Considering new Technology Entries and transfers to PIDS & FEP in 2007 Materials Section: Spin out a new cross-cut chapter on Emerging Research Materials. Memory Section: Will add NEMS mechanical memory to section. Divide Emerging Memory Tables into Resistive and Capacitive subcategories Update section in 2007 Logic Section: Considering reformulation of Logic Device Section to encourage high potential, but high risk approaches while maintaining Technology Entry evaluation function. Create subcategories for key Technology Entries (e.g. Spin & Molecular logic) Re-considering status of candidate Technology Entries (e.g. RSFQ Logic) Re-structuring Logic Section via Emerging Logic Workshop in September. Messages