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Sprinkler Buddy

Sprinkler Buddy. “Low Cost Irrigation Management For Everyone ! ”. Presentation #8: “Testing/Finalization of all Modules and Global Placement” 3/26/2007. Team M3 Kartik Murthy Panchalam Ramanujan Sasidhar Uppuluri Devesh Nema Kalyan Kommineni Design Manager: Bowei Gai.

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Sprinkler Buddy

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  1. Sprinkler Buddy “Low Cost Irrigation Management For Everyone ! ” Presentation #8: “Testing/Finalization of all Modules and Global Placement” 3/26/2007 Team M3 Kartik Murthy Panchalam Ramanujan Sasidhar Uppuluri Devesh Nema Kalyan Kommineni Design Manager: Bowei Gai

  2. CurrentStatus • Determine Project  • Develop Project Specifications  • Plan Architectural Design  • Determination of all components in design  • Detailed logical flowchart  • Design a Floor Plan  • Create Structural Verilog  • Make Transistor Level Schematic  • Layout • (~85% done..all modules LVS with only global left) • Testing (Extraction, LVS, and Analog Sim.) • (main modules verified)

  3. Finalized Floor Plan

  4. Transistor Count … Total: 30,817

  5. Updated Design Size • 330um x 335 um • ~ 1 : 1.01 aspect ratio • .11 mm^2 area • .28 Density

  6. Layout: Progress • All Big Modules LVS • Global Wiring still has to be finished • Control Logic locations estimated and placed • Needs wiring • Extracted Simulations Run on Major Blocks

  7. Layout : 60-20 MUX Density: .35transistors/um2

  8. Layout : ROMs ROM The decoder and ROM didn’t match at all… Decoder

  9. Layout : ROMs Changed Busses from M 1/2 to 3/4 Moved ROM under Bus

  10. Layout : Shifter Density: .35transistors/um2

  11. Layout : FP Add SIG Unit Inputs Density: .36transistors/um2 Outputs

  12. Layout : FP Add Exponent Unit Inputs Density: .34transistors/um2 Outputs

  13. Layout : FP Adder FSM Shaped to “Fill Gaps”

  14. Layout : FP Adder Inputs Density: .28transistors/um2 Outputs

  15. Layout : Floating Point Multiply Inputs Outputs Density: .34transistors/um2

  16. Layout : Entire Chip Density: .28transistors/um2

  17. Simulations : Extracted RC Mult Multiplier Output Clean Input Input Through Min Sized Inv 1.175ns propagation delay

  18. Simulations : Extracted RC Shifter Input Through Min Size Inv Clean Shift Signal Output from Shifter Output from Shifter 340ps propagation delay

  19. Design Challenges and Implementation DecisionsFor The Past Week

  20. Problems/Questions • Metal Directionality is lost when we rotate blocks • Possible to ignore this in blocks we don’t route over ? • Especially bad in large blocks (FP Adder) • Even worse to correct

  21. For Next Time • More Layout • Global Routing • Entire Chip Extracted RC Verification

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