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Sprinkler Buddy. “Low Cost Irrigation Management For Everyone ! ”. Presentation #5: “Transistor Level Schematics and Another Floor Plan” 2/21/2007. Team M3 Sasidhar Uppuluri Kalyan Kommineni Kartik Murthy Panchalam Ramanujan Design Manager: Bowei Gai. Current Status.
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SprinklerBuddy “Low Cost Irrigation Management For Everyone ! ” Presentation #5: “Transistor Level Schematics and Another Floor Plan” 2/21/2007 Team M3 Sasidhar Uppuluri Kalyan Kommineni Kartik Murthy Panchalam Ramanujan Design Manager: Bowei Gai
CurrentStatus • Determine Project • Develop Project Specifications • Plan Architectural Design • Determination of all components in design • Detailed logical flowchart • Design a Floor Plan (refined again) • Create Structural Verilog • Make Transistor Level Schematic (some control issues) • Layout • Testing (Extraction, LVS, and Analog Sim.)
Old (Naïve) Floor Plan Floor Plan
Transistor Count … Total = 30,397
New Design Size • 457um x 391 um • ~ 1 : 1.16 aspect ratio • .178 mm^2 area • .168 Transistor Density
Schematics: Read & Write to SRAM Read Write
Schematics: FP Units Multiplier Adder
Schematics: Control FP Adder Hourly Update
Design Challenges and Implementation DecisionsFor The Past Week
Problems/Questions • Small Problems with Control Logic in Schematic • Can we reduce more transistors with better logic ? • Any way to move the SRAM from the middle of our chip?
For Next Week • Perfect our Control Logic in the Schematic • Continue to reduce and optimize gates • Start Layout !
Some Other Slides For Reference…