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Sprinkler Buddy. “Low Cost Irrigation Management For Everyone ! ”. Presentation #7: “Redesign of Adder Parts And Layout of Other Major Blocks” 3/07/2007. Team M3 Kalyan Kommineni Kartik Murthy Panchalam Ramanujan Sasidhar Uppuluri Devesh Nema Design Manager: Bowei Gai.
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Sprinkler Buddy “Low Cost Irrigation Management For Everyone ! ” Presentation #7: “Redesign of Adder Parts And Layout of Other Major Blocks” 3/07/2007 Team M3 Kalyan Kommineni Kartik Murthy Panchalam Ramanujan Sasidhar Uppuluri Devesh Nema Design Manager: Bowei Gai
CurrentStatus • Determine Project • Develop Project Specifications • Plan Architectural Design • Determination of all components in design • Detailed logical flowchart • Design a Floor Plan • Create Structural Verilog • Make Transistor Level Schematic • Layout • (~65% done with all big modules except FP Add passing LVS …) • Testing (Extraction, LVS, and Analog Sim.) (ongoing…)
Transistor Count … Total: 32,921
Updated Design Size • 441um x 411 um • ~ 1 : 1.07 aspect ratio • .181 mm^2 area
Layout: Progress • Everything laid out has density > .3 transistors/um2 • All Big Modules LVS • FP Add is the exception • Had to redo many components • Initial layout was too big and messed up the floor plan • Currently done with all components except new shifter • New layouts enable us to match initial size estimate
Layout : Muxes Density: .42transistors/um2 1 bit 6 bit
Layout : Registers Density: .40transistors/um2 1 bit 10 bits
Layout : Register Enable Custom “AND” Gate
Layout : “Is Zero?” Unit Density: .41transistors/um2 • Sideways Inverters • Split NAND Gate
Layout : Leading Zero Counter Density: .40transistors/um2
Layout : Conditional Add/Sub Density: .30transistors/um2
Layout : Subtract Density: .33transistors/um2
Layout : New Barrel Shifter Still needs decoder and input buffers
Layout : FP Add Exponent Unit Inputs Density: .34transistors/um2 Outputs
Layout : FP Add Sig. Unit Inputs Density: .30transistors/um2 Outputs There is some wiring left and the shifter must be inserted
Layout : FP Adder Density: .33transistors/um2 Needs to be wired
Layout : Redone Integer Multiply So, why did we leave a HUGE hole? Density: .32transistors/um2
Layout : Floating Point Multiply Inputs Outputs Density: .31transistors/um2
Design Challenges and Implementation DecisionsFor The Past Week
Problems/Questions • We cannot accurately lay out our control logic until the FP Adder is done and global layout is all positioned
For Next Time • Lots and Lots more Layout • Finish the FP Adder • Place all blocks into global layout and fit control logic into the gaps • Global routing