Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program

1. Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program Tezaswi Raja Vishwani Agrawal Michael L. Bushnell Rutgers University, Dept. of ECE Piscataway, NJ 08854 Support from National Science Foundation, USA

2. Power in a CMOS Gate VDD = 5V IDD Ground VLSI Design Conf.

3. Problem Statement • Design a digital circuit for minimum transient energy consumption by eliminating hazards VLSI Design Conf.

4. Theorem 1 • For correct operation with minimum energy consumption, a Boolean gate must produce no more than one event per transition Ref: Agrawal, et al., VLSI Design’99 VLSI Design Conf.

5. Theorem 2 • Given that events occur at the input of a gate (inertial delay = d ) at times t1 < . . . < tn , the number of events at the gate output cannot exceed tn – t1 -------- d min ( n , 1 + ) tn - t1 + d time t1 t2 t3 tn tn + d Ref: Agrawal, et al., VLSI Design’99 VLSI Design Conf.

6. Minimum Transient Design • Minimum transient energy condition for a Boolean gate: | ti - tj | < d Where ti and tj are arrival times of input events and d is the inertial delay of gate VLSI Design Conf.

7. Linear Program (LP) • Variables: gate and buffer delays • Objective: minimize number of buffers • Subject to: overall circuit delay • Subject to: minimum transient condition for multi-input gates • AMPL, MINOS 5.5 (Fourer, Gay and Kernighan) VLSI Design Conf.

8. Limitations of This LP • Constraints are written by path enumeration. • Since number of paths in a circuit can be exponential in circuit size, the formulation is infeasible for large circuits. • Example: c880 has 6.96M constraints. VLSI Design Conf.

9. A New LP Model • Introduce two new timing windowvariables per gate output: • ti Earliest time of signal transition at gate i. • Ti Latest time of signal transition at gate i. t1, T1 ti, Ti . . . tn, Tn Ref: T. Raja, Master’s Thesis, Rutgers Univ., 2002 VLSI Design Conf.

10. New Linear Program • Gate variables d4 . . . d12 • Buffer Variables d15 . . . d29 • Corresponding window variables t4 . . . t29 and T4 . . . T29. VLSI Design Conf.

11. Multiple-Input Gate Constraints For Gate 7: T7> T5 + d7; t7 < t5 + d7; d7> T7 - t7; T7> T6 + d7; t7 < t6 + d7; VLSI Design Conf.

12. Single-Input Gate Constraints Buffer 19: T16 + d19 = T19 ; t16 + d19 = t19 ; VLSI Design Conf.

13. Overall Delay Constraints T11<maxdelay T12<maxdelay VLSI Design Conf.

14. Why New Model is Superior? • Path constraints from old model: 2 × 2 × … 2 = 2n paths between I/O pair • For new model, a single constraint controls I/O delay. Total variables, 24n. • New constraint set is linear in size of circuit. VLSI Design Conf.

15. Comparison of Constraints 6.96M Number of constraints 3,611 c880 Number of gates in circuit VLSI Design Conf.

16. Results: 1-Bit Adder VLSI Design Conf.

17. Estimation of Power • Circuit is simulated by an event-driven simulator for both optimized and un-optimized gate delays. • All transitions at a gate are counted as Events[gate]. • Power consumed  Events[gate] x # of fanouts. • Ref: “Effects of delay model on peak power estimation of VLSI circuits,” Hsiao, et al. (ICCAD`97). VLSI Design Conf.

18. Original 1-Bit Adder Color codes for number of transitions VLSI Design Conf.

19. Optimized 1-Bit Adder Color codes for number of transitions VLSI Design Conf.

20. Results: 1-Bit Adder • Simulated over all possible vector transitions • Average power = optimized/unit delay = 244 / 308 = 0.792 • Peak power = optimized/unit delay = 6 / 10 = 0.60 Power Savings : Peak = 40 % Average = 21 % VLSI Design Conf.

21. Results: 4-Bit ALU Power Savings : Peak = 33 %, Average = 21 % VLSI Design Conf.

22. Benchmark Circuits Circuit C432 C880 C6288 c7552 Maxdel. (gates) 17 34 24 48 47 94 43 86 Normalized Power No. of Buffers 95 66 62 34 294 120 366 111 Average 0.72 0.62 0.68 0.68 0.40 0.36 0.38 0.36 Peak 0.67 0.60 0.54 0.52 0.36 0.34 0.34 0.32 VLSI Design Conf.

23. Physical Design Gate l/w Gate l/w Gate l/w Gate l/w Gate delay modeled as a linear function of gate size, total load capacitance, and fanout gate sizes (Berkelaar and Jacobs, 1996). Layout circuit with some nominal gate sizes. Enter extracted routing delays in LP as constants and solve for gate delays. Change gate sizes as determined from a linear system of equations. Iterate if routing delays change. VLSI Design Conf.

24. Power Dissipation of ALU4 VLSI Design Conf.

25. References • R. Fourer, D. M. Gay and B. W. Kernighan, AMPL: A Modeling Language for Mathematical Programming, South San Francisco: The Scientific Press, 1993. • M. Berkelaar and E. Jacobs, “Using Gate Sizing to Reduce Glitch Power,” Proc. ProRISC Workshop, Mierlo, The Netherlands, Nov. 1996, pp. 183-188. • V. D. Agrawal, “Low Power Design by Hazard Filtering,” Proc. 10th Int’l Conf. VLSI Design, Jan. 1997, pp. 193-197. • V. D. Agrawal, M. L. Bushnell, G. Parthasarathy and R. Ramadoss, “Digital Circuit Design for Minimum Transient Energy and Linear Programming Method,” Proc. 12th Int’l Conf. VLSI Design, Jan. 1999, pp. 434-439. • M. Hsiao, E. M. Rudnick and J. H. Patel, “Effects of Delay Model in Peak Power Estimation of VLSI Circuits,” Proc. ICCAD, Nov. 1997, pp. 45-51. • T. Raja, A Reduced Constraint Set Linear Program for Low Power Design of Digital Circuits, Master’s Thesis, Rutgers Univ., New Jersey, 2002. VLSI Design Conf.

26. Conclusion • Obtained an LP constraint-set that is linear in the size of the circuit. LP solution: • Eliminates glitches at all gate outputs, • Holds I/O delay within specification, and • Combines path-balancing and hazard-filtering to minimize the number of delay buffers. • New LP produces results exactly identical to old LP requiring exponential constraint-set. • Results show peak power savings up to 68% and average power savings up to 64%. VLSI Design Conf.