Estimate power saving by clock slowdown for s5378 in 180nm and 32nm CMOS

1. Estimate power saving by clock slowdown for s5378 in 180nm and 32nm CMOS Chao Han ELEC 6270

2. Objective • Understand the influence of frequency in power and energy saving for certain CMOS technology (180nm and 32nm) • Understand the influence of frequency in power and energy saving between 180nm and 32nm CMOS technology

3. Theory • Ptotal = Ptran + Psc + Pstat • Ptran = α fck CVDD2/2 • Pstat = Isub VDD

4. Theory • Short-Circuit Energy Increases with rise and fall times of input. Decreases for larger output load capacitance. Decreases and eventually becomes zero when VDD is scaled down but the threshold voltages are not scaled down.

5. Circuit information S5378 • Number of inputs: 35 • Number of outputs: 49 • Number of DFFs: 179 • Number of gates: 2958 (counted in Powersim, one DFF counted as one gate) • Number of vectors: 10

6. Simulation Procedure • Use Matlab to convert Benchmark netliest into rugster netlist • Generate some random vectors as input signals • Set conditions and do the simulation

7. Simulation result

8. Simulation result Ptran(180nm)/Ptran(32nm)=4

9. Conclusion • Clock slowdown has impact in power saving not energy saving, and it is not significant when frequency becomes very slow because the leakage power becomes more important. • For 32nm CMOS technology, leakage power become extremely significant in proportion of the total power.

10. Future Work • Need to find other simulation tools to do the gate level power simulation • Try to use Hspice to do the transistor level power simulation based on some small circuit

11. Thanks! • question?