ITRS workshop on Emerging Spin and Carbon Based Emerging Logic Devices

1. ITRS workshop on Emerging Spin and Carbon Based Emerging Logic Devices George Bourianoff, Intel Jim Hutchby, SRC Barcelo Renacimiento Hotel Conference Room D2 Sept 17, 2010 (8:00 – 18:30) Seville, Spain

2. Outline • ERD charter • Background • Meeting Objectives • Next steps, timeline • Agenda

3. Charter of ERD Chapter On behalf of the 2011 ITRS, develop an Emerging Research Devices chapter to -- Critically assess new approaches to Information Processing technology beyond ultimate CMOS Identify most promising approach(es) to Information Processing technology to be implemented by 2024 To offer substantive guidance to – Global research community Relevant government agencies Technology managers Suppliers

4. Scope of ERD Chapter Integrated emerging research memory, logic and new architecture technologies enabled by supporting -- Materials and process technologies Modeling and simulation Metrologies Selection of specific technical approaches shall be Guided by fundamental requirements Bounded by ERD’s topic selection criteria

5. Scope of ERD ChapterCriteria for Including Technology Entries Devices and Architectures – Published by 2 or more groups in archival literature and peer reviewed conferences, or Published extensively by 1 group in archival literature and peer reviewed conferences Technology Entry (by itself or integrated with CMOS) must address a major electronics market. Materials and Fabrication Technologies – Materials and processes that address the specific material needs defined by emerging research device technology entries Supporting disciplines – specify for crosscut TWGs Metrologies Modeling & simulation

6. Emerging Research Devices Working GroupMeeting Objectives Review ERD/ERM 2010 Workshops (cont’d) Logic Devices Summary of VLSI Tech Workshop on III-V MOSFETs Assessment of III-V compound & Ge MOSFET technology Carbon-based nanoelectronic devices Spin Transfer Torque logic devices Review plans for ERD Device workshop in Seville, Spain on Sept. 17 Emerging Research Architectures (Logic device benchmarking) Current status Plans for 2010 – 2011 Summary of potential changes in 2011 ERD Chapter Summary of potential changes in 2011 ERM Chapter

7. Background • ITRS rewritten on a 2 year cycle • Information gathering workshops and chapter writing done on alternate years • 2010 is devoted to workshops • Previous Emerging Logic Workshop was held in Tsukuba, Japan 2008 focusing on spin and graphene devices • This workshop will review significant accomplishments in those areas in the intervening 2 years

8. Meeting objectives • Review significant new research initiatives in spin based logic • Review significant research programs and accomplishments in graphene based logic • Hold brief business meeting • Discuss 2011 ERD Logic Table structure and en tries • Discuss potential writing assignments

9. 8:00 Welcome and Introductions G. Bourianoff 8:15 Overview of DARPA Spin Logic Program D. Shenoy 8:50 Nano-magnetic Logic S. Hu 9:25 All Spin Logic B. Bhin-Aein 10:00Break 10:15 Magnetic FPGA Spin in Logic T. Hanyu 10:50 "TIMARIS" Linear dynamic deposition technology W. Maass for production of spintronic devices 11:25 Wrap-up and Discussion G. Bourianoff 12:00 Lunch Morning AGENDAProgress, status and research needs for spin based logic elements – Sept, 17, 2010

10. 13:15 Graphene Logic Devices P. Kim 13:50 Analog & RF Graphene – based FETs C.Y. Sung 14:20 GRAND Perspectives on Graphene Electronics H. Kurz 15:00 Break 15:15 Gate induced Bandgap for Graphene Devices T. Tsukagoshi 15:50 Graphene Research at CEA S. Roche 16:25 Wrap-up and Discussion J. Hutchby 17:00 Break 17:30 ITRS Business Meeting J. Hutchby 18:30 Adjourn Afternoon AGENDAProgress, status and research needs for graphene based logic elements – Sept. 17, 2010

11. Business meeting

12. Emerging Research Logic Device business meeting • Review table structure and make recommendations • 2009 had 3 tables plus transition table • Table 1 MOSFETS: Extending the channel to the End of the Roadmap • Table 2 Charge based Beyond CMOS: Non-Conventional FETs and other Charge-based information carrier devices • Table 3 Alternative Information Processing Devices • Review table entries and make recommendations

13. New Logic Technology Tables Table 1 – MOSFETs Extending the Channel of MOSFETs to the End of the roadmap _____________ CNT FETs Graphene nanoribbons III-V Channel MOSFETs Ge Channel MOSFETs Nanowire FETs Non conventional geometry devices Table 3 - Non-FET, Non Charge-based ‘Beyond CMOS’ devices _______________ Collective Magnetic Devices Moving domain wall devices Atomic Switch Molecular Switch Pseudo-spintronic Devices Nanomagnetic (M:QCA) Table 2- Unconventional FETS, Charge-based Extended CMOS Devices _______________ Tunnel FET I-MOS Spin FET SET NEMS switch Negative Cg MOSFET

14. 2009 Logic Transition table

17. Issues and Decisions for 2011 Chapter - Logic Logic (Baltimore): The following questions were addressed:1. Is the new organization (e.g. 3 subsections) an effective taxonomy of logic devices? 2. Are the technology entries the best candidates pursed by the research community? 3. Any technology entries in the logic chapter to move to the transition table? Potential candidates for 2011? 4. Right level of details? Mission accomplished concerning current status and critical paths? Refer to Adrian Ionescu’s presentation for his thoughtful answers to these questions (attached to this file). • In the Logic Transition Table, the IN/OUT entries for Ge FET, Spin MOSFET, Collective Spin Devices, Pseudomorphic, and Nanomagnetic Devices should be move into the Comment column to the right. Entries in the IN/OUT column might better be technical in nature. (being considered & discussed)

18. Issues and Decisions for 2011 Chapter - Logic • Areas for improvements (suggested by Adrian Ionescu): • Introduction of energy efficiency criteria? Important (being considered/discussed) • Role of other functionality than digital of beyond CMOS: image processing, analog, RF, etc. (being considered/discussed) • Convergence of beyond CMOS and More than Moore technology entries? MEMS/NEMS already in (being considered/discussed) • More interaction with emerging architectures needed. (Decided) • Transfer to PIDS in 2011 • Alternate channel materials , Ge and III-V Semiconductors (keep CNT and GNR FETs) (Decided) • Unconventional FET s, Tri-Gate, FinFET, GAA FETs, etc. (Decided) Logic (Hsinchu): • Transfer to PIDS in 2011 • Alternate channel materials , Ge and III-V Semiconductors (keep CNT and GNR FETs) (Decided) • Unconventional FET s, Tri-Gate, FinFET, GAA FETs, etc. (Decided)

19. Memory Technology Entries Resistive Memories • Nanoelectromechanical • Spin Transfer Torque MRAM • Macromolecular (Polymer) • Molecular Memory • Nanothermal • Thermochemical FUSE/Anti-FUSE • Nanowire PCM • Nanoionic Memory (Electrochemical) • Cation migration • Anion migration • Electronic Effects Memory • Charge trapping • Metal-Insulator Transition • FE barrier effects Capacitive Memory • FeFET Memory

20. Issues and Decisions for 2011 Chapter - Memory Memory (Baltimore): • In the Memory Section, we need to discuss fabrication and issues related to the select device, either a diode or a transistor, for the storage elements in a cross-bar array. • We will include emerging research solid state Storage Class Memory technologies, but not include SCM based on mechanical or magnetic disc storage. The driving issue is to minimize the cost per bit – this is very important. Memory (Hsinchu): No decisions

21. Proposed changes to the ERD Memory section • To take out the “electronic effect memories” entry from the ERD memory table • The FTJ memory could be covered along with FeFET as a subcategory • Mott Memory could form a stand-alone entry if the ERD group decides, there is a sufficient critical mass of works