ALU (Continued)

1. ALU(Continued) Computer Architecture(Fall 2006)

2. ALU Notation • An ALU is denoted using the following graphical notation. Operand1 (A) Operand2 (B) 8 8 Indicates number of bits on each line ALU 9 4 Result Operation

3. Selecting 2 Registers • ALU needs 2 operands to work! • How to select 2 registers from a Register File? 8 8 M U X 1 M U X 2 Register File 00 00 8 8 01 01 8 8 10 10 8 8 11 11 8 2 8 2 Register Select 1 Register Select 2 Operand1 Operand2

4. ALU with Inputs Mux2 Register File (4) 8 Mux1 8 8 What do we do with results or output from the ALU? ALU 2 2 8 4 Results Operation Operand1 Operand2

5. ALU Output • Solution: Put it into a register! • OK, so do we do that? • That is, Given 1 input how to route it on n different paths? 8 Register 1 00 8 8 Register 2 01 DeMux Result from ALU 8 Register 3 10 8 Register 4 11 2 Select Inputs

6. Handling ALU Output A Each device has its own selection logic typically specified using a truth table! (Note that this is not a single Mux but 8, 4x1 Muxs) Mux2 Register File (4) Flags Clock 32 DeMux B Mux1 8 8 ALU 2 2 2 8 4 Operand1 Operation Operand2 Destination

7. Data path • The ALU and associated components constitute the Data Path • Includes Registers, Multiplexers and any other device associated with ALU operations • All operands are typically the same size • Register sizes match with size of operand • Size of operands are associated with CPU • 32-bit processor (ALU uses 32-bit operands) • 64-bit processor (ALU uses 64-bit operands)

8. Handling Constant Values • Earlier data path did not permit initialization of registers with constant values • Limited constant values could be achieved using operations supported by ALU. • Even that was pretty convoluted! • Solution: Add instruction to initialize register • With a constant value • Typically, the constant value is embedded as a part of the instruction. • By reusing as many bits as possible for this task

9. Implementation Strategy • Fix code for constant value initialization • Have to use a code that is not already used by ALU • In our case, let’s set it to 1111 for our ALU • If initialization is detected, use constant bits in instruction to initialize a register. • Need 8-bits to hold constant value for 8-bit CPU • For this we can reuse register selection input bits to double up as constant bits in this instruction as we are not using registers for any operation. • Need 2-bits to select 1 of 4 destination registers

10. Handling Constants A Mux2 Register File (4) Flags 8 8 8 DeMux B 1 0 Mux Mux1 8 8 ALU 4 4 4 8 4 4 Operand1 Operand2 Destination This Mux chooses between data from registers or the 8 bits from the instruction depending on the operation. If the operation is to store a constant then the ALU simply passes the constant bits as its output. The constant bits are then pushed to the DeMux and are finally stored in the register indicated by destination This is not a special device but just a notation to show the lines are being combined Where do these bits actually come from? 4 Operation

11. Where do instructions come from? • The data path uses a set of bits that constitute an instruction • Where do these instruction bits come from? • Solution: Memory • A large collection of words • Each word consists of 1 or more bytes (8-bits) • Similar in philosophy as a Register File • Manufactured using different technology • Makes it slower • But a whole lot cheaper!

12. Memory Organization Revisited D E M U X Memory Slot 0 M U X Bi-directional Data lines 16 Memory Slot 1 16 • • • Memory Slot n Note that any memory slot can be read or written to by providing suitable bit patterns (or Addresses) for the selection lines to the Mux and De-Mux. In other words, memory slots can be Randomly accessed. Consequently, such memory organizations are called Random Access Memory (RAM) Read (RD) Selection Lines 8 Tri-state Buffer: Special device that disables the line so that the same wire can be used for reading or writing (bi-directional)!

13. Memory-ALU Interconnection • Typically memory is large in size • Gigabytes in size these days • Cannot be packed into the CPU • Cost prohibitive • Memory is manufactured separately • Interconnected with the CPU using Buses • Buses are long wires interconnecting devices • Particularly ALU Data Path & Memory • Buses for memory • Address Bus: Selection lines for Mux and De-Mux • Data Bus: Bits to be written into memory locations.

14. Abstract Notation for Memory Address Bus carries bits for Selection lines (Mux & De-Mux). These bits are called Addresses! Uni-directional Address Bus Memory (RAM) Size of each Slot X Number of Slots (16 x 256) Note the relationship between the Memory configuration and the number of lines in the Address and Data Buses. 8 Enable (EN) Read/Write (RD) Logic 16 Bi-directional Data Bus

15. Using Memory • Memory has 3 primary inputs • Address Bus carrying address of memory slot • Indicates which memory slot to read or write • Data Bus (The actual data bits to be stored or read) • Control signals (Read/Write & Enable) • How to wire these inputs & outputs to the ALU data path? • Design requirements • Need to store output from ALU • Need to load data from memory into ALU • Need to load instructions from memory into ALU We need go provide Addresses to the Memory unit in order to do these operations!

16. Tackling Addresses • Address is used to select a memory slot • For fetching instructions • In an repetitive manner • Typically from consecutive locations • Think of it as an Array in Java! • Need to somehow generate the addresses • Typically done using some register in the ALU to store intermediate results • For reading/writing data at random addresses • Address depends on the instruction at hand • The instruction typically needs to identify the address to read or write. // Assume each instruction is 16-bits long short memory[256]; for (int address = 0; (address < 256); address++) { instruction = memory[address]; process(instruction); }

17. Address Generation Logic Circuit • Issues to consider & solutions • Address needs to be generated by adding 1 • Use a ripple carry adder to add • Addresses need to be stored before/after add • Use a register • Need alternate between address for instructions and address for storing/reading data • Use a multiplexer for choosing • Use a Clock to drive the selection lines of this multiplexer • Select address for instruction first (Clock = 0). • Select address for reading/writing data next (Clock = 1).

18. Catch! • Our data path is not symmetric • Instructions are 16-bits wide • Data or Registers are 8-bits wide • How do we design a memory module that can • Provide 16-bits first • Provide 8-bits next • It is going to take some work • Use the lowest denominator memory module • One than can provide 1 byte at a time • Assemble bytes together to make instructions

19. Working with Bytes… Address Bus Instruction Data Chip Enable RD Byte 3 Byte 1 Byte 2 8 Memory (8 x 256) De-Mux 00 01 1X 8 Data Bus S1 S0 1 Instruction / Data Byte Select Least significant address bit changes between 0 and 1 for each consecutive address. When the clock is low (S1=0) the De-Mux places the bytes read from Memory into Byte1 and Byte2 depending on S0 (so S0, the least significant bit from the address bus) which switches between 0 and 1 when clock is low to fetch two bytes from memory.. When the clock is high (S1=1), the De-Mux ignores s0 and places the data read from memory into Byte 3.

20. Design Considerations • Address needs to be generated to fetch instructions from memory • Typically one of the registers hardwired to the data path is reused for this purpose • This register is typically called • Program Counter • Instruction Pointer • In the sample data path Reg3 is being used as the instruction pointer • Using a register eases handling conditional and unconditional branching in programs • These are used to achieve if and looping constructs in high level languages • Also used for managing subprograms/methods/functions in a high level languages

21. Adding Memory to Data path 1 Mux 0 Register File (3) Reg3 Flags Latch * 8 Mux1 Mux2 + R W 8 8 8 32 110 EN RD Address Bus DeMux Memory (8 X 256) 1 0 Mux B 8 A 8 Delay to generate 2 clock pulses from 1. This causes 110 to be added to Reg3 two times for each clock pulse. 8 R Mux * ALU 2 2 0 1 6 8 8 2 Data Bus 8 4 * W * OP Code Operand1 Operand2 Destination Data Latch 8 01 DeMux 00 11

22. Branching • Branching is achieved by simply resetting value in Register R3 with a suitable address • Note that R3 ultimately determines address from where next instruction is fetched for processing. • Can be achieved in two ways • Load a constant in to R3 • Add a different constant (other than 1) in the address generation circuit. • Assign a new OPCode for this operation, say: 110000

23. Branching Circuit 8 8-bit Adder Temp Reg Reg3 Address Bus 8 8 8 8 110 Mux7 0 Clock Multiplier 8-bit Constant from Instruction 1 8 2 Sel. OpCode (1100) 2 Clock Input Select to add constant address only when clock is 1 because until such time, the constant value is not yet sable! This circuit adds 110 to the address of next instruction stored in Reg3 normally. However, in a branch instruction, rather than adding 110 this logic circuits adds a constant value specified in the instruction causing the address for the next instruction to change. The constant can be positive or negative (2’s comp). Similar approach is used for conditional branching as well!

24. Conditional Branching • Branching based on conditions • Used to implement if..then constructs • Constant branch address is added only if some condition is true • In our case let’s do a simple example involving the carry flag generated by the ALU • Introduce new OPCode (say 1110) • Change address (in Reg3) only if Carry Flag is 12.

25. Conditional Branching Circuit 8 8-bit Adder Temp Reg Reg3 Address Bus 8 8 8 8 110 Mux7 0 Clock Multiplier 8-bit Constant from Instruction 1 8 Sel. Carry Flag (1 bit) + OpCode (1110) 3 1 2 OpCode (1100) Generates a 1 when OPCode=1110 and CarryFlag = 1 Only when Clock is 1 2 Clock Input