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LEON SPARC V8 Processor

OUTLINE. FeaturesConfigurationSynthesisCustomizationInterfacing with ZBT RAMSoftware IssuesLeon MP. Features. Implements a 32-bit SPARC V8 processor.Separate instruction and data caches, hardware multiplier and divider, interrupt controller Debug Support Unit (DSU) with trace buffer, two 2

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LEON SPARC V8 Processor

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    1. LEON SPARC V8 Processor Amitoj Cheema Ajay Bhutani

    2. OUTLINE Features Configuration Synthesis Customization Interfacing with ZBT RAM Software Issues Leon MP

    3. Features Implements a 32-bit SPARC V8 processor. Separate instruction and data caches, hardware multiplier and divider, interrupt controller Debug Support Unit (DSU) with trace buffer, two 24-bit timers, two UARTs 16-bit I/O port, flexible memory controller, Ethernet MAC ,PCI interface. New modules can easily be added using the on-chip AMBA AHB/APB buses.

    4. Integer Unit 5 stage pipelined configurable number of Register Windows (2 - 32). Default setting of 8. Up to four watchpoint registers configured. Aids Software Debugging Can cause a trap on an arbitrary instruction or data address range. If DSU is enabled, the watchpoints can be used to enter debug mode.

    5. Debug Support Unit(DSU) Allows non-intrusive debugging on target hardware. insert breakpoints and watchpoints access to all on-chip registers from a remote debugger( GDB etc) Trace buffer to trace the executed instruction flow Can monitor AHB bus traffic. Communicates to an outside debugger using a dedicated UART or through a AHB master (PCI) Can load software into processor

    6. Others Memory interface Very flexible memory interface to PROM, memory mapped I/O, SRAM,SDRAM). Introduce wait states Flexible data width (8,16 or 32 bit) Through MCFG1 and MCFG2 Registers AMBA AHB APB Buses PCI Interface Ethernet MAC

    7. OUTLINE Features Configuration Synthesis Customization Interfacing with ZBT RAM Software Issues Leon MP

    8. Configuration Methods Graphical (Easy) Manual (more powerful) Leon/device.vhd

    9. Important Choices (Graphical) Synthesis -> Infer ROM For ADM-XRC board ( Virtex 2) Process -> DSU Boot Options Internal Prom Read / Write wait states -> 1 System Frequency -> 33000000 Baud Rate Pabits -> 8

    10. Configuration using Device.vhd Provides more configuration options than graphical Configure AHB Master/Slave address space PCI bus address space options Memory Controller additional Configurations Presently Graphical Configuration for LEON-MP not available.

    11. OUTLINE Features Configuration Synthesis Customization Interfacing with ZBT RAM Software Issues Leon MP

    12. Synthesis Whole synthesis using Xilinx ISE tools EDIF2NGD tool doesn’t work properly Synplify Synthesis doesn’t work Many template boards configurations available in Leon distribution for common boards. Hecht-xcv800 for Xess board

    13. Synthesis Flow

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