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Sub-Threshold Standard Cell Tool

Sub-Threshold Standard Cell Tool. Purpose. Save power Scale down power rail Ensure Reliability Issues with variation Issues with timing Identify and Replace Use custom cell Use different cell from library. How it works. Tool Flow. Function.

cmcginley
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Sub-Threshold Standard Cell Tool

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  1. Sub-Threshold Standard Cell Tool

  2. Purpose • Save power • Scale down power rail • Ensure Reliability • Issues with variation • Issues with timing • Identify and Replace • Use custom cell • Use different cell from library

  3. How it works Tool Flow Function Uses Perl to open path and write celllist.lst Skill and Perl work together to generate schematic with all cells Start Cadence and collect info with log file

  4. How it works (cont’d) Tool Flow Function Skill Creates secondary library of cells for testing Big ocean created with Perl which contains test information for each cell Ocean runs and creates individual results Perl script checks outputs

  5. Standard Cell Testing The figure below displays a typical testing setup for a cell from the ST 120 library. Another thought to keep in mind is the timing of the waveforms of the inputs.

  6. A Thought about Variability Want a process TT (typical N&P) to sit on the balanced process line These effects are amplified due to the exponential dependence on current in sub-threshold SF corner is a worst case scenario in P-Strong (left box) FS corner is the worst case scenario in N-Strong (right box)

  7. Cell Results ST Micro 90 (715 cells) St Micro 120 (698 cells) Includes D FF’s & D latches Tested at Tmin = 2 uSec Vdd FF TT SS FS SF .35 22 25 29 10 35 .3 25 25 28 8 41 .25 25 27 27 8 41 .2 25 29 29 8 41 Includes D FF’s & D latches Tested at Tmin = 2 uSec VddFF TTSSFSSF .35 20 20 18 15 24 .3 17 21 21 15 35 .25 20 20 20 15 49 .2 22 19 21 13 57

  8. Cell Results (cont’d) ST Micro 90 (715 cells) St Micro 120 (698 cells) Not Including D FF’s & D latches Tested at Tmin = 2 uSec Vdd FF TT SS FS SF .35 5 5 5 5 5 .3 5 5 5 5 5 .25 5 5 5 5 5 .2 5 5 13 8 5 Not Including D FF’s & D latches Tested at Tmin = 2 uSec VddFF TTSSFSSF .35 4 4 4 4 5 .3 4 4 4 4 5 .25 4 4 4 4 5 .2 4 4 4 4 5

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