A Variation-tolerant Sub-threshold Design Approach

1. A Variation-tolerant Sub-threshold Design Approach Nikhil Jayakumar Sunil P. Khatri . Texas A&M University, College Station, TX

2. Motivation • In recent times, chip power consumption has become a significant hurdle • Higher power consumption leads to • Shortened battery life • Higher on-chip temperatures – reduced operating life of the chip • There is a large and growing class of applications that where power reduction is paramount – not speed • Such applications are ideal candidates for sub-threshold logic

3. Sub-threshold Leakage • As supply voltage scales down, the VT of the devices is scaled down as well • A lower VTresults in exponentially higher leakage • Leakage power is becoming comparable with dynamic power • A larger VT would reduce leakage but increase delay • We can turn this dilemma into an opportunity !!

4. The Opportunity • Performed simulations for 2 different processes on a 21 stage ring oscillator • Impressive power reduction (100X – 500X) • PDP improves by as much as 20X • Delay penalty can be reduced by several means • Applying forward body bias • Decreasing VT • Circuit approaches

5. The Opportunity • We also performed experiments with lower VT values • Delays improved with decreasing VT values, as expected • PDP remained high • Power gains decreased with decreasing VT values

6. Sub-threshold Logic • Advantages • Circuits get faster at higher temperature. Hence reduced need for expensive cooling techniques • Device transconductance is an exponential function of Vgs which results in a high ratio of on to off current. Hence noise margins are near-ideal • Disadvantages • Ids exhibits an exponential dependence on temperature • Ids also has a strong dependency on process variations (such as VT variations) • Ids is small

7. Previous Approaches • Paul et al (2001) reported a sub-threshold multiplier • Compensation of Ids over P/T variations • Tschanz et al (2002) discuss a dynamic body bias technique to make design process variation tolerant • Applied in the context of regular CMOS technologies • Circuit delay matched to critical delay (hard to determine) • Matching is performed for entire design monolithically • In contrast to these, we: • Compensate sub-threshold delayover P/V/T variations • Apply our compensation to a network-of-PLA design • Critical delay is trivially determined • Perform compensation separately for clusters of spatially nearby PLAs

8. Our Solution • We propose a technique that uses self-adjusting body-bias to phase-lock the circuit delay to a beat clock • Use a network of dynamic NOR-NOR PLAs to implement circuits • Regular, area and delay efficient approach • PLAs partitioned into clusters of 1000 PLAs each • All PLAs in a cluster share bulkn node • Arepresentative PLA in the cluster is chosen to phase lock the delay of the cluster to the beat clock • Beat clock period determines circuit speed • bulkn voltage modulated via charge pump • If the delay is too high, a forward body bias is applied to speed up the PLA, and vice versa

9. Dynamic NOR-NOR PLA • We use precharged NOR-NOR PLAs as the structure of choice • Wordlines run horizontally • Inputs / their complements and outputs run vertically • Several PLAs in a cluster share a common bulkn node • Each PLA has a “completion” signal that switches low after all the outputs switch Outputs Inputs completion clk clk

10. The Charge Pump - PLA “completion” signal lags beat clock - bulkn node gets forward biased pullup pulldown - PLA “completion” signal leads beat clock - bulkn goes back to zero bias

11. Effectiveness of the Approach • We simulated a single PLA over 0 to 100oC. We also applied VT variations (10%) and Vdd variations (10%) • The light region shows the variations on delay over all the corners • The red region shows the delays with the self-adjusting body-bias circuit

12. Example Showing Phase Locking • This figure shows how the body bias (and hence the delay of the PLA) changes with changes in VDD • Note PLA delay remains relatively constant • The adjustment is very quick (within a clock cycle) VDD changed from 0.22 to 0.18V VDD changed from 0.2 to 0.22V

13. Summary • Sub-threshold circuit design is promising due to extreme low power consumption • 100 – 500X power reduction, 10 – 25X speed penalty • Appealing for a widening class of applications • However, it is inherently not tolerant to PVT variations • Our approach dynamically compensates for PVT variations • Lock delay of a representative PLA in a cluster, to a beat clock • Use a charge pump which modulates nbulk bias voltage • Dramatic reduction in sensitivity to PVT variations • This can help achieve a significant yield improvement

14. Thank you!!