1 / 18

Variation immunity in sub-threshold operation

Variation immunity in sub-threshold operation. Patricia Gonzalez Divya Akella VLSI Class Project. Motivation : Sub-threshold Operation . Sub-threshold processor which runs on 180mV [1] Sub-threshold FPGAs A sub-VT ring oscillator at 80mV [2].

zoltin
Download Presentation

Variation immunity in sub-threshold operation

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Variation immunity in sub-threshold operation Patricia Gonzalez DivyaAkella VLSI Class Project

  2. Motivation : Sub-threshold Operation • Sub-threshold processor which runs on 180mV [1] • Sub-threshold FPGAs • A sub-VT ring oscillator at 80mV [2]. • A 65nm chip : 256kb memory in sub-threshold region to below 400mV [3] • New wireless applications : Wearable body sensor node (19uW) running on harvested energy – small devices, long lifetimes! Ultimate aim ? Reduce Power consumption!

  3. Variation In sub-threshold • Taken from [1] B. Calhoun • Issue : Meet Throughput • 100 operations every 5 seconds -> Frequency requirement

  4. Motivation : Yield • a critical obstacle : sensitivity of sub-threshold circuits to variations in process, voltage, and temperature (PVT) • Affects delay : limits product yield ! • A system that adjusts the chip operation to account for PVT ?

  5. Motivation : Razor • System should be able to run at multiple frequencies and voltages. • Design to ensure correct operation at all PVT variations. • Variations ? Environmental, local, global, voltage droops, even data dependent! • Razor approach : DVS based on dynamic detection of errors

  6. Motivation : PDVS • Voltage reduced to minimum voltage possible. • Headers allow to dither between voltages. • Different energies for different modes of operation/workload!

  7. The Problem • First “high” input is caught by the flop : seen at output Q • Second “high” input is missed ?

  8. Test circuit • To experiment with this problem : chose a 3 bit adder • Output is shown to be flopped

  9. Solution • Shadow latch • Error comparator

  10. Waveform

  11. System

  12. Overhead ? • Power consumption of razor circuit : • Worst case (FF) corner power at 0.4 V = 1.4 nW • Further optimization is definitely possible! • Use of razor circuit only for critical paths

  13. Design • Typically – corner analysis to select a supply voltage ? • Extra margin for worst case scenario! • What if variability is rare , what if it never occurs ? • In lower processes and sub – threshold , variability might be so much – voltage margins go up! • Optimization during circuit design can now be done for a typical case • We attempt to show use of razor in sub-threshold voltages.

  14. Savings example (T = 20C) V (3 freqof operation) % savings 0.4 31.81% 0.425 21.99% 0.45 14.21% 0.475 0.5 38.21% 0.55 25.49% 0.6 18.32% 0.65 0.7 42.49% 0.8 29.24% 0.9 15.08% 1

  15. A Perspective of Yield • Variable voltage and frequency to adjust to variation • It will improve the efficiency, thereby increasing yield and lowering costs. • Achievable performance for a given energy budget • Improve yield at a given frequency by allowing slower chips to speed up by going to higher VDD • Yield against process variation !!

  16. 40 MHz 200 kHz 100 kHz

  17. References [1] Wang, A.; Chandrakasan, A.; , "A 180mV FFT processor using subthreshold circuit techniques," Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International , vol., no., pp. 292- 529 Vol.1, 15-19 Feb. 2004 2] B. H. Calhoun and A. Chandrakasan, “Characterizing andModeling Minimum Energy Operation for Subthreshold Circuits,” in ISLPED, 2004, pp. 90–95. [3] B. Zhai, et al., “Theoretical and Practical Limits of Dynamic Voltage Scaling,” in DAC, 2004, pp. 868–873. [4] Dan Ernst, Tao Phan. Razor : A low power pipeline based on Circuit Level timming speculation. [5] Mathias Eireiner,. In situ Delay Characterization and Local Supply voltage adjustment for compensation of local parameter variations.

  18. Gate leakage based timer : • Intended to use it as a clock source • Did not integrate into the system • Originally, used as a timer in the sub – Hz range • Gate leakage based system – variation with temperature is reduced • Found that with varying capacitance charging time, leakage transistors and Schmitt trigger design – higher frequency ranges can be obtained. Voltage Time period Frequency 0.4 3.71E-07 2.70E+06 0.5 5.65E-08 1.77E+07 0.6 1.40E-08 7.16E+07 0.7 5.16E-09 1.94E+08 0.8 2.54E-09 3.94E+08 0.9 1.54E-09 6.48E+08 Can be used as an unstable source of clock on chip, with possible caliberation with a stable clock source.

More Related