Memory Technologies

1. Memory Technologies EE 454 Embedded Architectures

2. ROM • ROM – values in bits of words “programmed” at construction time • PROM – programmable ROM values in bits can be programmed by zapping components (e.g. diodes) after construction with a high voltage • EPROM – electrically programmable ROM • EEPROM – Electrically erasable programmable ROM • Flash memories – EEPROM in which erasing is done in large blocks (blocks are erased in a flash)

3. ROM structure

4. Two-dimension Decoding

5. EPROM • Programmed by an electronic device that supplies higher voltages than those normally used in digital circuits. • Erased only by exposing it to strong ultraviolet light

6. EPROM with floating gate MOS transistor • Floating-gate • Not connected • Surrounded by high-impedance material • Program it • Put high-voltage on non-floating gate • Negative charge leaks to floating gate (hot carriers injection) • Change of threshold voltage • Guaranteed to retain 70% of charge for ten years (non-volatile!)

7. EPROM packages

8. Static RAM Cell • RAM – Random Access Memory • Sequential access devices?? • ROMS are random access also • Static RAM Cell • D flip-flop with control logic fig 9-20 SEL_L=0, WR_L=1 Read SEL_L=0 & WR_L=0 Write

9. 8x4 static RAM • Notes • SRAM – static RAM • 3 addr lines  ___ words • __ bits per word • WE_L • CS_L • OE_L • DIN3 -

10. Static RAM timing - READ

11. Static RAM timing - WRITE

12. Bidirectional Bus • Bidirectional bus – read and write on same lines

13. Synchronous Static RAM - SSRAM • Clocked interface for control, address, and data • Synchronized with clock signal on bus • Latches save addr, control, data lines on rising edge • AREG, CREG, INREG • Operation performed during subsequent cycle

14. Timing of SSRAM

15. Dynamic RAM • Static RAM Cell • D flip-flop + control = 6 transitors • Dynamic RAM • 1 transistor • 1 capacitor • Operation • Reading • Writing • Capacitor leaks  refreshing required

16. Synchronous DRAM Structure

17. Refreshing • Charge stored in the capacitor leaks out • Needs to be refreshed • Refresh Cycle ~ 64 milliseconds • Refresh an entire row at a time • E.g. newer RAMs have • 4096 rows • Refreshed once every 64 ms • 64ms/4096 = one row every 15.6 μs

18. Varieties of RAMS • Static – fastest most expensive used for caches • Dynamic RAM • SDRAM – synchronous DRAM (clock from bus/CPU) • DDR SDRAMs - Double data rate – transfers data on both edges of the clock

19. Embedded Systems Memory Types (http://www.netrino.com/Embedded-Systems/How-To/Memory-Types-RAM-ROM-Flash) SRAM or DRAM? EEPROM or flash? What types of memory will you use in your next embedded systems design?

20. As memory technology has matured in recent years, the line between RAM and ROM has blurred. • Referred to as hybrid memory devices. • Read and written as desired, like RAM, but • Maintain their contents without electrical power, just like ROM.

21. Two of the hybrid devices, EEPROM and flash, are descendants of ROM devices. These are typically used to store code. • The third hybrid, NVRAM, is a modified version of SRAM. NVRAM usually holds persistent data.

22. EEPROMs • electrically-erasable-and-programmable ROMs. • Similar to EPROMs, but the erase operation is accomplished electrically, rather than by exposure to ultraviolet light. • Any byte within an EEPROM may be erased and rewritten. Once written, the new data will remain in the device forever--or at least until it is electrically erased.

24. Flash memory • Combines the best features of the memory devices described thus far. • High density, low cost, nonvolatile, fast (to read, but not to write), and electrically reprogrammable. • The use of flash memory has increased dramatically in embedded systems. • Very similar to EEPROM. The major difference is that flash devices can only be erased one sector (256 bytes to 16KB)

25. NOR Flash memories(http://en.wikipedia.org/wiki/Flash_memory) • Reading from NOR flash is similar to reading from random-access memory, • can be executed directly without the need to first copy the program into RAM. NOR flash may be programmed in a random-access manner similar to reading. • Programming changes bits from a logical one to a zero. • Reset all the bits in the erased block back to one. Typical block sizes are 64, 128, or 256 KB. • For sequential data writes, NOR flash chips typically have slow write speeds compared with NAND flash.

26. NAND flash • NAND flash architecture was introduced by Toshiba in 1989. • The reduction in ground wires and bit lines allows a denser layout and greater storage capacity per chip. • Forms the core of the removable USB storage devices • These memories are accessed much like block devices such as hard disks or memory cards.

27. NAND flash • While reading and programming is performed on a page basis, erasure can only be performed on a block basis. • Data in a block can only be written sequentially. • NAND is best suited to systems requiring high capacity data storage. This type of flash architecture offers higher densities and larger capacities at lower cost with faster erase, sequential write, and sequential read speeds, sacrificing the random-access and execute in place advantage of the NOR architecture.

28. NVRAM (non-volatile RAM) • Usually just an SRAM with a battery backup. • When the power is turned on, the NVRAM operates just like any other SRAM. • When the power is turned off, the NVRAM draws just enough power from the battery to retain its data. • NVRAM is fairly common in embedded systems. However, it is expensive--even more expensive than SRAM, because of the battery— • applications are typically limited to the storage of a few hundred bytes of system-critical information that can't be stored in any better way.

29. Characteristics of the various memory types