Future Memory Technologies in Nano Era

1. Future Memory Technologies in Nano Era Kinam Kim, Hongsik Jeong* Semiconductor R&D Center Samsung Electronics Co. Ltd.

2. Contents • Introduction • Opportunities and Reality of New Types of Memories • Technology Scaling and Technology Barriers of New Memories • 1) FRAM • 2) MRAM • 3) PRAM • 4. Summary

3. History of Memory Device 1947 : The invention of Transistor - William B. Shockley, John Bardeen and Walter H. Brattain at The Bell Laboratories - Nobel Prize, 1956 1951 : The invention of BJT 1955 : The invention of FET 1958-9: First Integrated Circuit - Jack Kilby at Texas Instruments ( 2000, Nobel Prize ) Robert Noyce at Fairchild Camera 1966 : Invention of DRAM Paper Clip, Ge 1970 : Intel, 1Kb DRAM D/R = 8 m World First Transistor : Point Contact Memory Density : X 1,000,000 Feature Size : X 1/100 2004 : Samsung, 1Gb DRAM D/R = 0.08 m

4. ? ? 512Gb 100nm 100 1st Node 3rd Node 2nd Node 256Gb FLASH 100 80 1.41  / year 64Gb DRAM -5nm / year Design Rule [nm] 55nm 60 32Gb Density [Gb] 8Gb 10 40 4Gb 25nm 1Gb 20 10nm 1 512Mb 2000 2005 2010 2015 2020 Memory Scaling Trend • Growing technical complexity, fabrication cost, physical limit • What are showstoppers? Year

5. Electric field distribution Maximum electric field Gate contact ( V/cm ) Scaling Limit of DRAM • Cell transistor scaling Channel length decrease → Channel doping increase → Electric field increase → Junction leakage current increase → Retention time decrease

6. Cell Transistor Technology • 3D Cell Structure reducing E-Field Planar Transistor RCAT ( Recessed Cell TR.) FINFET Tr.

7. V6 Control gate V4 ONO CFGCG CFGY VCG CFGXY CFGX VFG Floating gate V1 V2 CFGX V5 CFGY CONO V3 STI CTUN Tunnel oxide Silicon substrate Scaling Limit of NAND Flash • Cell-to-cell coupling Narrower word-line space → Cell-to-cell capacitance increase → Wide distribution of Vth → Over-program / under-erase

8. Scaling Limit of NAND Flash • Cell-to-cell coupling estimation • Steep increase of coupling • below 40 nm • Improvement : • - Low-k dielectric • - Floating gate height scale • down.

9. Memory & Device Fundamental limiting factor Limit of technology node DRAM Cell transistor scaling 50 nm NAND Flash Cell to cell interference 20 nm NOR Flash Si-SiO2 barrier height 50 nm SRAM CMOS 10 nm CMOS Electron wave length 10 nm Scaling Limit of Memories • Lifetimes of conventional memories are far shorter than that of CMOS • Need new memories with longer lifetime, less technical barriers and better functional properties

10. Contents • Introduction • Opportunities and Reality of New Types of Memories • Technology Scaling and Technology Barriers of New Memories • 1) FRAM • 2) MRAM • 3) PRAM • 4. Summary

11. Characteristics of Emerging New Memories • New Paradigm of IT World requires Ideal Memory • - New Materials and New Function Devices New Function • Non-volatility • : > 10 years • Fast random access • : tRead = 10ns tWrite = 5ns ~ 100ns • Virtually unlimited usage • : > 10^12 cycles New Material • FRAM: Ferroelectric Material PZT, SBT, BLT… • MRAM: Ferromagnetic Material NiFe, CoFe,… • PRAM: Chalcogenide GeSbTe,…

12. Opportunities of New Memories • Memory management in systems • complicated multiple memory  simplified single memory • Reduce power consumption – mobile system • High Speed Data Storage • Merge code and data storage memory • Simplify data changing process Block write (flash)  bit-by-bit write enhance system performance • Virtually unlimited endurance No need for complicated software • New applications – Instant on PC, …

13. New Memory Applications Mobile Devices • Simplified Data Process / No Buffer Memory  New Memory Solution  Flash + RAM Solution

14. NOR Flash NAND Flash New Memory New Memory Applications High Speed Data Storage • The Reduction of Data Storage Time (7sec  7ms) • The Comparison of 2Mb Pixel Picture Storage Time - VGA, 640x480, 420KB Block Erase  Program : 7000ms 1x 245ms 35x 1,000x 7ms The possibility of Motion Picture or Continuous Taking Photos

15. Emerging Memory Devices MRAM ( Magnetic RAM ) PRAM ( Phase-Change RAM ) FRAM ( Ferroelectric RAM ) Cell Sw. Speed High Speed (~10ns) High Speed (~10ns) Moderate Speed ( >100ns ) Density Low Density Very Low Density High Density Potential Tunnel Ox. Control ( <10A) Switching Current Cell to Cell Disturbance Reduction of Cell Current Key Features Reliability of Capacitor

16. Parameter DRAM SRAM NAND Flash NOR Flash FRAM MRAM PRAM Nonvolatile no no yes yes yes yes yes Random access yes yes no yes yes yes yes Write cycles >1015 >1015 105 105 >1013 >1015 >1013 Read time 10 ns 2 ns 25 s 70 ns 70 ns 10 ns 10 ns Write time 10 ns 2 ns 300 s 10 s 70 ns 5 ns 200 ns Comparison of Memory Characteristics

17. DRAM SRAM NAND Flash NOR Flash FRAM Memory capacity 1Gb 64 Mb 2 Gb 128 Mb 256 Kb Tech. node 90 nm 100 nm 90 nm 120nm 350 nm Cell Area Factor (F2) 8 90 5.3 11 80 Commercially available memories • New types of memories are only at the early stage of verification or creating niche market, despite its great potentials • FRAM passed the criteria of commercial product but its density is still very low

18. Contents • Introduction • Opportunities and Reality of New Types of Memories • Technology Scaling and Technology Barriers of New Memories • 1) FRAM • 2) MRAM • 3) PRAM • 4. Summary

19. WL F-Cap. BL Technology Scaling of FRAM • Cell area scaling 1. Larger capacitor area for given footprint 2. Larger remnant polarization 3. Thinner ferroelectric film • Nonvolatile •  loose constraint on array transistor

20. Cell Area Scaling of FRAM 25F2 15F2 6F2 ~ 8F2 3-mask etch Separate via & plate 700nm cap stack 1-mask etch Common via & plate 300nm cap stack 3D capacitor Etchless capacitor

21. Technology Barriers of FRAM • Ferroelectric film thickness scale down • Degradation of electrical and physical properties • Lower thickness limit  few nm ? • Need new growth technique!

22. Technology Barriers of FRAM • Reliability requirement - Endurance > 1014 cycles - Retention time > 10 years @ 85C 50nm thick MOCVD PZT on Ir Deposition Temp. : 530o C Fatigue stress : 2.5V@1MHz 125oC Bake

23. Contents • Introduction • Opportunities and Reality of New Types of Memories • Technology Scaling and Technology Barriers of New Memories • 1) FRAM • 2) MRAM • 3) PRAM • 4. Summary

24. Rp Rap Rap Rp NiFe Al2O3 CoFe MRAM Operations Magnetic tunneling resistance variation depending on relative magnetization directions of electrode

25. 2. Immunity to writing disturbance Resistance uniformity Easy axis field Write Window Hard axis field (Oe) Requirements for proper operations R Distribution Reference Sensing noise 1.0 PDF 0.5 “0” “1” 0.0 8 10 12 14 16 R ( k W ) • Only MTJs at the crosspoint of bit-line • and digit-line should be switched • - Small ditribution of switching field • - Asteroid curve close to L-shape • Large MR ratio • Small distribution of resistance

26. Rap – Rp Rp • TMR ratio = Technology Barriers of MRAM • Small sensing signal • Maximum TMR ratio ? 60% so far. • Resistance variation • Exponential dependence on Al2O3 thickness

27. Operating condition Possible fail with Disturbance Technology Barriers of MRAM • Writing Disturbance Need to decrease switching field distribution - Roughness - MTJ shape - MTJ aspect ratio - Free layer magnetization - Free layer thickness

28. 2 m 1.2x0.6 m 2 m 0.8x0.4 m 2 m 0.4x0.2 m 200 100 Bit line field (Oe) 0 BL -100 0.2m 0.45m DL -200 -100 -50 0 50 100 Digit line field (Oe) Technology Barriers of MRAM • Scaling trend of writing current • Smaller MTJ size  Higher switching field  Higher writing current - Power consumption increase - Chip size increase - Reliability issues • Improved by flux concentrating layer NiFe

29. Prospects for MRAM • Nearly ideal memory - Non-volatile, fast read and write, unlimited endurance • Many technical barriers • Scaling issues – large cell size - SOC chip application is more suitable than stand-alone memory application

30. Contents • Introduction • Opportunities and Reality of New Types of Memories • Technology Scaling and Technology Barriers of New Memories • 1) FRAM • 2) MRAM • 3) PRAM • 4. Summary

31. Top Electrode Crystalline Temp Amorphizing BEC RESET Pulse (~few ns) Tm Bottom Electrode Crystallizing Top Electrode SET Pulse ~50ns Amorphous Tx BEC Low resistance SET state : “0” High resistance RESET state : “1” Bottom Electrode Time PRAM Operations • Reversible phase change of chalcogenide (Ge2Sb2Te5) • Phase change by heating current control

32. (m ) (m2 ) (m ) (NMOS Cell Tr) Cell area scaling • PRAM density vs writing current • Need enough cell transistor width to flow required writing current • Cell area is mainly determined by cell transistor width

33. 3.5 3.0 Reset Current ( mA ) 2.5 2.0 1.5 0.66x1.28 0.72x0.72 0.66x0.66 0.62x0.62 0.56x0.56 0.48x0.48 0.40x0.40 GST Size Technology Barriers of PRAM • Large writing current - Require large cell transistor  Cell area increase - Reliability degradation - Current scales down with contact and GST size !

34. M1 TEC BE GST BEC M0 PRAM Writing Current Reduction • Edge contact cell • Contact area is controlled by BE thickness & width •  more small and uniform contact area • Reset current reduction by more than 80%

35. Prospects for PRAM • Writing current reduction – new structure, new material • Intrinsic advantage for size scaling - High density Feasibility - Stand-alone memory with moderate speed (Possibility of NOR flash replacement)

36. Contents • Introduction • Opportunities and Reality of New Types of Memories • Technology Scaling and Technology Barriers of New Memories • 1) FRAM • 2) MRAM • 3) PRAM • 4. Summary

37. Summary • Assessment of memory products - We need to consider functional and cost aspects at the same time - Functional aspect : random access, speed, non-volatility, endurance, … - Cost aspect : technical complexity, technical barrier, technology scaling • Prospects for Conventional memories - Non-ideal functional aspects - Excellent cost aspects - Will be dominant players down to 30~50nm technology node

38. Summary • Prospects for New types of memory - Manufacturing and cost aspects are not properly evaluated yet 1) FRAM : No serious limitations in theory except ferroelectric film thickness 2) MRAM : Excellent device characteristics, Scaling difficulty  Suitable for SOC chip application 3) PRAM : Less technical barriers compared to FRAM and MRAM Intrinsic advantage for size scaling - Future of emerging memory depend on how far we can keep its key attributes ( ferroelectric cap in FRAM, MTJ in MRAM, reset current in PRAM)