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Review on Emerging Memory Technologies for Universal Memory Integration

This literature review analyzes various emerging memory technologies like PRAM, STTRAM, and RRAM, aiming for universal memory integration. The challenges and potentials of each technology are discussed, along with a comparison of their features and limitations.

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Review on Emerging Memory Technologies for Universal Memory Integration

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  1. Literature Review on Emerging Memory Technologies Fengbo Ren Apr. 1st 2011

  2. Background • Existing Memory Technology • Scaling become very difficult at and below 45-nm • SRAM suffers leakage • DRAM’s capacitor need to sustain enough charges • Flash needs novel array structure SRAM DRAM Flash

  3. Background • Dream about “Universal Memory” • Fast read and write speed of SRAM • Density and cost benefits of DRAM • Non-volatility of flash • Unlimited endurance Resistive RAM Phase Change RAM Spin Torque Transfer RAM

  4. Basic Concept — PRAM • Represents “0/1” by Crystalline and Amorphous T > crystallization point High R Low R Ge2Sb2Te5 (GST) High T > melting point 0 1

  5. Basic Concept — STTRAM • Represents “0/1” by Magnetization Direction Alignment Ferro-magnetic Materials Anti-parallel Parallel Magnetic Tunnel Junction(MTJ) Write High current, fast switching, bigger cell size Low RP High RAP Write Low current, Slow switching, smaller cell size Read Read

  6. Basic Concept — RRAM • Represents “0/1” by resistance difference of dielectric - V High R Low R Over Drive Metal Oxides Wearing + V

  7. State-of-Art Comparison • PRAM • Flash density & endurance + Fast R/W speed • STTRAM • SRAM density & R/W speed + Highest endurance • RRAM • <SRAM density & R/W speed + High endurance

  8. Challenges—PRAM • Resistance and threshold voltage drift over time • Cause chip failure in long term • Limits the ability for multilevel operation • Speed vs. data retention time • If the switching thermal condition is close to standby condition, e.g. room temperature • Faster switching speed — intended switching • Worse data retention time — higher probability of accidental switching • Sensitive to temperature • Narrower operation window (0-70°C )

  9. Challenges—STTRAM • The switching current required is still too high. • 1-8x106 A/cm² • Typical transistor:105-106 A/cm² • Bigger transistor size -> bigger cell size -> poor density • Boosting voltage -> higher power • Switching energy of MTJ is 2-3 orders of magnitude bigger than a CMOS gate • Lower switching current is desired • Low Rhigh/Rlow ratio • 5x is the highest ratio reported, 2-3x in practical • Small sensing margin for reading • Lower switching current -> even smaller sensing margin

  10. Challenges—RRAM • Need to understand the physics • Conduction filament formation & broken mechanism • Resistance & resistance variation dependency on bias voltage • Wearing mechanism • Build precise compact model for CAD flow • Significant resistance variation • Worse sensing margin • Deteriorate the multi-level operation capability

  11. Conclusion • PRAM • Flash density & endurance + < Flash R/W speed • Nice replacement of Flash, commercial product is available • STTRAM • SRAM density & R/W speed + Highest endurance • Require better MTJ with smaller switching current to achieve higher density • RRAM • Initial stage of exploration • <SRAM density & R/W speed + High endurance • Potential of multi-level operation • Lot of studies need to be done

  12. Thank You! • References [1] F. Tabrizi, ”The future of scalable STT-RAM as a universal embedded memory”, Available: http://www.eetimes.com/design/embedded/4026000/The-futureof-scalable-STT-RAM-as-a-universal-embedded-memory. [2] S. Kang, et al., ”A 0.1-m 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation”, JSSC, vol. 42, no. 1, pp. 210–218, 2007. [3] K.J. Lee, et al., ”A 90 nm 1.8 V 512 Mb Diode-Switch PRAM With 266 MB/s Read Throughput”, ISSCC, 2008, pp. 150–162. [4] G. Servalli, ”A 45nm generation Phase Change Memory technology”, IEDM, 2009, pp. 1–4. [5] G. De Sandre, et al., ”A 4 Mb LV MOS-Selected Embedded Phase Change Memory in 90 nm Standard CMOS Technology”, JSSC, vol. 46, no. 1, pp. 52–63, 2011. [6] M. Hosomi, et al., ”A Novel Nonvolatile Memory with Spin Torque Transfer Magnetization Switching: Spin-RAM”, IEDM, 2005, pp. 459–462. [7] Takayuki Kawahara, et al., ”2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read”, ISSCC, 2008, pp. 109–120. [8] C.J. Lin, et al., ”45nm Low Power CMOS Logic Compatible Embedded STT MRAM Utilizing a Reverse-Connection 1T/1MTJ Cell”, IEDM, 2009, pp. 1–4. [9] R. Nebashi, et al., ”90nm 12ns 32Mb 2T1MTJ MRAM”, ISSCC, 2009, pp. 462–463. [10] David Halupka, et al., ”Negative-Resistance Read and Write Schemes for STT-MRAM in 0.13m CMOS”, ISSCC, 2010, pp. 256–257. [11] Kenji Tsuchida, et al.,”A 64Mb MRAM with Clamped-Reference and Adequate-Reference Schemes”, ISSCC, 2010, pp. 258–259. [12] K. Tsunoda, et al., ”Low Power and High Speed Switching of Ti-doped NiO ReRAM under the Unipolar Voltage Source of less than 3 V”, IEDM, 2007, pp. 767–770. [13] H.Y. Lee, et al., ”Low Power and High Speed Bipolar Switching with A Thin Reactive Ti Buffer Layer in Robust HfO2 Based RRAM”, IEDM, 2008, pp. 1–4. [14] H.Y. Lee, et al., ”Evidence and solution of Over-RESET Problem for HfOX Based Resistive Memory with Sub-ns Switching Speed and High Endurance”, IEDM, 2010, pp. 19.7.1–19.7.4.

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