An Introduction to Structural Style Coding in VHDL

1. An Introduction to Structural Style Coding in VHDL

2. Structural Style: From Digital Circuit to VHDL For structural style coding, we need to define all the hardware components individually. To explain the process, we show a general, yet important example, and proceed step by step. Problem. Suppose that a digital circuit diagram is given. Give the corresponding VHDL code. NB: In such a problem, we can use the IEEE libraries for defining the gates. We may also need to consult the hardware documentation to ensure that we use the correct functions that will map to an efficient synthesis. For example, we need to make sure that we use any internal multipliers in the FPGAs …

3. The First Steps in VHDL We can use the IEEE standard package for the basic gate definitions: library IEEE; use IEEE.std_logic_1164.all; We next specify the interface of the circuit using an entity command and the connections between the gate components. The solution follows …

4. Solution Procedure (I/II) 1. Recognize all the necessary libraries. 2. Recognize all the inputs and outputs for the circuit. Define the interface of the circuit using: entitycircuitName is port (IN0, IN1, … : in std_logic; Out0, Out1, … :out std_logic); end circuitName; 3. Name all the gates or hardware components (eg:And_1, And_2, …, Or_1, Or_2,…, Inv_1, Inv_2, ). 4. For all internal connections, we need to name the wires. We can use the names of the gates that they connect to come up with intuitive names.Eg. For the connection from And2 to Inv3, we can name the wire as Αnd2toInv3.

5. Solution Procedure (II/II) 5. Recognize the gate types that we need using component commands: component And2 port (I0, I1: in std- logic; O: out std-logic); end component; component And3 port (I0, I1, I2 : in std- logic; O: out std-logic); end component; etc 6. Define all the interconnections using component commands. Eg. To connect And2 toInv3, use: And_2: And2 port map (Iname1, Iname2, And2toInv3) Inv_1: Inv3 port map (And2toInv3, OutName);

6. An Example To implement the following digital circuit, we follow the solution procedure. IN_0 IN_1 OUT_0 IN_2 IN_3

7. Recognize the Inputs and Outputs IN_0 IN_1 OUT_0 IN_2 IN_3 Inputs: IN_0, IN_1, IN_2, IN_3. Outputs: OUT_0. We will use them with the entity command!

8. Recognize and Define the Hardware And_1 IN_0 IN_1 Or_1 Inv_1 OUT_0 And_2 IN_2 IN_3 Gates: And_1, And_2 of two inputs and a single output. Or_1 of two inputs and a single output. Inv_1 inverter. ... they will have to be defined using component commands and we must also define each gate separately in the architecture definition.

9. Define the Signals for All Internal Connections Inv_1_to_Or_1 And_1 IN_0 And_1_to_Inv_1 x IN_1 Or_1 Inv_1 x OUT_0 x And_2 And_2_to_Or1 IN_2 IN_3 Signals: And_1_to_inv_1, Inv_1_to_Or_1, And_2_to_Or_1. ... will be defined using the signal command. Also, to implement the circuit, we use the given circuit diagram.

10. Implementation of the Circuit library IEEE; use IEEE.std_logic_1164.all; entity Comb_eg is port (IN_0, IN_1, IN_2, IN_3: in STD_LOGIC; OUT_0: out STD_LOGIC); end Comb_eg; architecture Comb_eg is signal And_1_to_Inv_1, And_2_to_Or1, Inv_1_to_Or_1: STD_LOGIC; component inv port (I: in STD_LOGIC; O: out STD_LOGIC); end component;

11. component and2 --“and” gate with two inputs from IEEE. port (IN_0, IN_1: in STD_LOGIC; OUT_0: out STD_LOGIC); end component; component or2 --“or” gate with two inputs from IEEE libraries. port (IN_0, IN_1: in STD_LOGIC; OUT_0: out STD_LOGIC); end component; begin -- implementation of the circuit Inv_1: inv port map (And_1_to_Inv_1, Inv_1_to_Or_1); And_1: and2 port map (IN_0, IN_1, And_1_to_Inv_1); And_2: and2 port map (IN_2, IN_3, And_2_to_Or1); Or_1: or2 port map (Inv_1_to_Or_1, And_2_to_Or1, OUT_0); end Comb_eg;