Modeling and design of on-chip inter-block decoupling capacitors for PSN and EMI reduction

1. Modeling and design of on-chip inter-block decoupling capacitors for PSN and EMI reduction Josep Rius1and Maurice Meijer2 UPC 1 Departament d’Enginyeria Electrònica Universitat Politècnica de Catalunya, Spain 2 Digital Design and Test Group Philips Research Laboratories, The Netherlands

2. gate switching time [ps] ~ 10cm ~ cm ~mm 10 Featuresize[nm] Power supply PCB Package Chip … 45 70 100 130 …. Motivation EMI high frequency content of PSN Small gate switching times Dimensions comparable to the wavelength of the HF components • On-chip decoupling capacitors (decaps) • Effective solution to reduce power supply noise (PSN) • Decreases current loops thereby reducing EMI • Design constraints: performance, leakage, … This work concerns a model and design procedurefor on-chip MOS decaps targeting PSN and EMI reduction

3. rG = poly gate resistance r= channel resistance c = gate tochannel capacitance cB = channel to substrate capacitance rB = substrate resistance i(v) = direct tunneling gate current Proposed Decap Model NMOS decap: l VDD ALL PARAMETERS ARE PER UNIT LENGTH GND GND rG c i(v) r p+ p+ n+ n+ (B) cB rB substrate • Model characteristics: • Distributed RGC model to take into account HF effects • Gate leakage modeled by a voltage-dependent current source

4. rG = poly gate resistance r= channel resistance c = gate tochannel capacitance cB = channel to substrate capacitance l rB = substrate resistance VDD i(v) = direct tunneling gate current GND GND c i(v) r p+ p+ n+ n+ (B) rB substrate Proposed Decap Model (cnt’d) NMOS decap: ALL PARAMETERS ARE PER UNIT LENGTH • Model simplification: • Exploit symmetry of the decap • Poly gate resistance (rG) << channel resistance (r) • Channel-to-substrate capacitance (CB) neglected

5. VDD v(x,t) r, c i(v) GND x -l l 0 MOS Decaps: Analytical Solution Diffusion equation with proper boundary and initial conditions Channelterm Gate leakageterm Steady-state response can be separated into DC+AC solution

6. Example DC response. Drop voltage along the channel increases as tOX is reduced Drop voltage along the channel increases with channel length l = 10mm , w = 3mm, w = 3mm, 65nm CMOS 90nm CMOS l = 5mm l = 10mm 65nm CMOS 45nm CMOS l = 20mm +l +l 0 0 Normalized voltage along the channel Normalized distance alonga half of channel length

7. Normalized voltage along the channel Normalized voltage along the channel Normalized voltage along the channel d d d l 0 L 0 0 L Example AC response. No leakage case 1.1 1 VM ejwt r, c 0.9 v(x,t) d d x 0.8 0 -l +l maximum effective decap length  Amplitude A(x) changes along the channel. It depends on r and c as well as w

8. Normalized voltage along the channel Normalized voltage along the channel Normalized voltage along the channel d dL L 0 l 0 d 0 L Example AC response. Leakage case 1.1 1 VM ejwt r, c g 0.9 v(x,t) d d x 0.8 0 -l +l Now dLcan be approximated by Amplitude A(x) changes along the channel. It depends on r , cand g as well as w

9. Input Impedance of a MOS Decap l r, c g ZIN • Critical frequency at l= • The frequency that separates lumped and distributed behaviour • Lower critical frequency in case of gate oxide leakage LEAKAGE: NO LEAKAGE:

10. Normalized R and C as a function of frequency

11. Intra-block and Inter-block MOS decaps • Intra-block decaps have constrained dimensions • For example, the are implemented in the standard-cell template • Inter-block decaps do not suffer from this constraint • Typically, used for EMI reduction purposes System-on-Chip Digital logic block

12. (A) (B) LF LF LF LF LF LF LF VDD Y VDD WS GND GND Y VDD VDD Z Z Z Z Z Z Z Z Z Example Inter-Block Decap: Gate length must be limited

13. Example Inter-Block Decap: Fingers and Stripes Finger VDD GND Stripe VDD GND Stripe VDD

14. Inter-Block Decap Model Parameters • Model parameters are defined to be independent of length and width Channel sheet resistance [W/□] Gate capacitance per unit area [F/m2] Gate oxide conductance per unit area [S/m2] Gate current density per unit area [A/m2] Total gate area [m2] Critical frequency Total gate-oxide leakage

15. Procedure for Optimum Inter-Block Decap Design 1. Define the total decoupling capacitance CDEC to be included in the IC 2. Determine the effective total area as 3. Obtain the gate length of a finger LF0 to get the maximum frequency fC for which the decap needs to perform 4. Define the number of gate fingers as 5. Obtain the gate length of a single decap as 6. Define the number of stripes as where WMAX is the maximum allowed gate width 7. Obtain the gate width of a single decap as 8. Calculate total leakage

16. Example Total decap area vs. fC red : tox = 6.5 nm magenta: tox = 5 nm black: tox = 1.6 nm • 90nm GP technology • Required decap CDEC = 1nF • Three gate-oxide thicknesses Gate length of a finger vs. fC red : tox = 6.5 nm magenta: tox = 5 nm black: tox = 1.6 nm • Results: • Area factor = 1.01 to 1.23 • Total leakage current • ILEAK = 1.1 mA

17. Conclusions • Distributed decap model based on physical grounds • Relevant parameters for each technology node are easily obtained • Such parameters are independent of dimensions for inter-block decaps • Critical Frequency fC qualifies decoupling performance • Defines the border between full and reduced decap performance • Relevant expressions have been derived • Simple procedure to design inter-block decaps based on the proposed model