SoC Verification ( 晶片系統驗證 )

1. SoC Verification (晶片系統驗證) Pao-Ann Hsiung (熊博安) hpa@computer.org http://www.cs.ccu.edu.tw/~pahsiung/ 嵌入式系統實驗室 國立中正大學資訊工程學系

2. Contents • Introduction 3 ~ 26 • Formal Verification 27 ~ 38 • Model Checking 39 ~ 73 • Equivalence Checking 74 ~ 83 • Verification Tools 84 ~ 86 • Verification Example:Industrial Embedded SoC 87 ~ 98 • Conclusion & Future Work 99 ~ 100 Pao-Ann Hsiung, CSIE, National Chung Cheng University

3. Introduction 1998 1999 2001 Process Technology 0.25 um 0.18 um 0.15 um Silicon Complexity 1 M Gates 2~5 M Gates 5~10 M Gates M O O R E’ S L A W Deep Sub-Micron (DSM) Technology Pao-Ann Hsiung, CSIE, National Chung Cheng University

4. Introduction Challenges in DSM technology for SoC: • Timing Closure • Sensitive to interconnect delays • Large Capacity • Hierarchical design and design reuse • Physical Properties • Signal integrity (crosstalk, IR drop, power/ground bounce) • Design integrity (electron migration, hot electron, wire self-heating) Pao-Ann Hsiung, CSIE, National Chung Cheng University

5. Introduction Gates / Chip Design Productivity Gap Gates / Hour 1990 1995 2000 Pao-Ann Hsiung, CSIE, National Chung Cheng University

6. Introduction Time-to-Market (TTM) Trends Pao-Ann Hsiung, CSIE, National Chung Cheng University

7. Introduction • Multiple Design Disciplines: • Digital HW • Embedded SW • Analog/Mixed Signal (AMS) Blocks • Bus Architectures • Clock / Power Distributions • Test Structures Pao-Ann Hsiung, CSIE, National Chung Cheng University

8. Introduction SoC Verification v/s Design Gap Pao-Ann Hsiung, CSIE, National Chung Cheng University

9. Verification Options • Simulation Technologies • Static Technologies • Formal Technologies • Physical Verification and Analysis Pao-Ann Hsiung, CSIE, National Chung Cheng University

10. Simulation Technologies • Event-based Simulators • Cycle-based Simulators • Transaction-based Simulators • Code Coverage • HW/SW Co-verification • Emulation Systems • Rapid Prototyping Systems • Hardware Accelerators • AMS Simulation Pao-Ann Hsiung, CSIE, National Chung Cheng University

11. Static Technologies • Lint Checking • Syntactical correctness • Identifies simple errors • Static Timing Verification • Setup, hold, delay timing requirements • Challenging: multiple sources Pao-Ann Hsiung, CSIE, National Chung Cheng University

12. Formal Techniques • Theorem Proving Techniques • Proof-based • Not fully automatic • Formal Model Checking • Model-based • Automatic • Formal Equivalence Checking • Reference design  modified design • RTL-RTL, RTL-Gate, Gate-Gate implementations • No timing verification Pao-Ann Hsiung, CSIE, National Chung Cheng University

13. Physical Verification & Analysis Issues for physical verification: • Timing • Signal Integrity • Crosstalk • IR drop • Electro-migration • Power analysis • Process antenna effects • Phase shift mask • Optical proximity correction Pao-Ann Hsiung, CSIE, National Chung Cheng University

14. Comparing Verification Options Pao-Ann Hsiung, CSIE, National Chung Cheng University

15. Comparing HW/SW Coverification Options Pao-Ann Hsiung, CSIE, National Chung Cheng University

16. Which is the fastest option? • Event-based simulation • Best for asynchronous small designs • Cycle-based simulation • Best for medium-sized designs • Formal verification • Best for control-oriented designs • Emulation • Best for large capacity designs • Rapid Prototype • Best for software development Pao-Ann Hsiung, CSIE, National Chung Cheng University

17. SoC Verification Methodology • System-Level Verification • SoC Hardware RTL Verification • SoC Software Verification • Netlist Verification • Physical Verification • Device Test Pao-Ann Hsiung, CSIE, National Chung Cheng University

18. SoC Verification Methodology Pao-Ann Hsiung, CSIE, National Chung Cheng University

19. Verification Approaches • Top-Down Verification • Bottom-Up Verification • Platform-Based Verification • System Interface-Driven Verification Pao-Ann Hsiung, CSIE, National Chung Cheng University

20. Top-Down SoC Verification verification Pao-Ann Hsiung, CSIE, National Chung Cheng University

21. Bottom-Up SoC Verification verification Components, blocks, units Memory map, internal interconnect Basic functionality, external interconnect System level Pao-Ann Hsiung, CSIE, National Chung Cheng University

22. Platform Based SoC Verification Derivative Design • Interconnect Verification between: • SoC Platform • Newlyadded IPs Pao-Ann Hsiung, CSIE, National Chung Cheng University

23. System Interface-driven SoC Verification Besides Design-Under-Test, all others are interface models Pao-Ann Hsiung, CSIE, National Chung Cheng University

24. Device Test • To check if devices are manufactured defect-free • Focus on structure of chip • Wire connections • Gate truth tables • Not functionality Pao-Ann Hsiung, CSIE, National Chung Cheng University

25. Device Test Challenges in SoC device test: • Test Vectors: Enormous! • Core Forms: soft, firm, hard, diff tests • Cores: logic, mem, AMS, … • Accessibility: very difficult / expensive! Pao-Ann Hsiung, CSIE, National Chung Cheng University

26. Device Test Strategies • Logic BIST (Built-In-Self-Test) • Stimulus generators embedded • Response verifiers embedded • Memory BIST • On-chip address generator • Data generator • Read/write controller (mem test algorithm) • Mixed-Signal BIST • For AMS cores: ADC, DAC, PLL • Scan Chain • Timing and Structural compliance • ATPG tools generate manufacturing tests automatically Pao-Ann Hsiung, CSIE, National Chung Cheng University

27. Formal Verification

28. What is Formal Verification? • An analytic way of proving a system correct • no simulation triggers, stimuli, inputs • no test-benches, test-vectors, test-cases • Deductive Reasoning (theorem proving) • Model Checking • Equivalence Checking Formal Verification Methods Pao-Ann Hsiung, CSIE, National Chung Cheng University

29. Theorem Proving • Uses axioms, rules to prove system correctness • No guarantee that it will terminate • Difficult, time consuming: for critical applications only Pao-Ann Hsiung, CSIE, National Chung Cheng University

30. Model Checking • Automatic technique to prove correctness of concurrent systems: • Digital circuits • Communication protocols • Real-time systems • Embedded systems • Control-oriented systems • Explicit algorithms for verification Pao-Ann Hsiung, CSIE, National Chung Cheng University

31. Equivalence Checking • Checks if two circuits are equivalent • Register-Transfer Level (RTL) • Gate Level • Reports differences between the two • Used after: • clock tree synthesis • scan chain insertion • manual modifications Pao-Ann Hsiung, CSIE, National Chung Cheng University

32. Why Formal Verification? • Simulation and test cannot handle all possible cases (only some possible ones) • Simulation and test can prove thepresenceofbugs, rather than theirabsence • Formal verification conducts exhaustive exploration of all possible behaviors • If verifiedcorrect, all behaviors are verified • If verifiedincorrect, a counter-example (proof) is presented Pao-Ann Hsiung, CSIE, National Chung Cheng University

33. Why Formal Verification Now? • SoC has a high system complexity • Simulation and test are taking unacceptable amounts of time • More time and efforts devoted to verification (40% ~ 70%) than design • Need automated verification methods for integration into design process Pao-Ann Hsiung, CSIE, National Chung Cheng University

34. Increased Simulation Loads Pao-Ann Hsiung, CSIE, National Chung Cheng University

35. Why Formal Verification Now? Examples of undetected errors • Ariane 5 rocket explosion, 1996 • Exception occurred when converting 64-bit floating number to a 16-bit integer! • Pentium FDIV bug • Multiplier table not fully verified! Pao-Ann Hsiung, CSIE, National Chung Cheng University

36. Pao-Ann Hsiung, CSIE, National Chung Cheng University

37. Verification Tasks for SoC Pao-Ann Hsiung, CSIE, National Chung Cheng University

38. Property Checking v/s Equivalence Checking Pao-Ann Hsiung, CSIE, National Chung Cheng University

39. Model (Property) Checking • Algorithmic method of verifying correctness • of (finite state) concurrent systems • against temporal logic specifications • A practical approach to formal verification Pao-Ann Hsiung, CSIE, National Chung Cheng University

40. Model Checking What is necessary for Model Checking? • A mathematically precise model of the system • A language to state system properties • A method to check if the systemsatisfies the given properties Pao-Ann Hsiung, CSIE, National Chung Cheng University

41. Model Checking • Formal model of the system • Finite State Machine (FSM) • Desired behavior expressed as a set of properties (specifications) • Computation Tree Logic (CTL) • Method to check properties against system • Efficient FSM traversals Pao-Ann Hsiung, CSIE, National Chung Cheng University

42. Formal Models of System Any mathematically precise model that can be represented as a state transition system • Finite State Machines • Petri Nets • (Timed) Automata • Statecharts Pao-Ann Hsiung, CSIE, National Chung Cheng University

43. State Transition System M(S, R, L) S = {s1, s2, s3} R = transition relation L = {a, b, c} s1 a ac b s2 s3 Kripke Structure Pao-Ann Hsiung, CSIE, National Chung Cheng University

44. Formal Model v/s Verification • 表達能力 v/s 驗證複雜度 找平衡點! 語言的表達能力 表達能力豐富 表達能力簡單 Undecidable nonelementary EXPSPACE EXPTIME PSPACE 驗證問題複雜度 NP PTIME Pao-Ann Hsiung, CSIE, National Chung Cheng University

45. Property Specification Languages • Linear Temporal Logic (LTL) • Computation Tree Logic (CTL) • Timed Computation Tree Logic (TCTL)  7 ms Pao-Ann Hsiung, CSIE, National Chung Cheng University

46. CTL – Computation Tree Logic • Path quantifiers • A(for all computation paths) • E (for some computation path) • Temporal operators • X (next time, next state) • F (eventually, finally) • G (always, globally) • U (until) • R (release, dual of U) Pao-Ann Hsiung, CSIE, National Chung Cheng University

47. CTL Formulas • Temporal logic formulas are evaluated with respect to a state in the model • State Formulas • Apply to a specific state • Path Formulas • Apply to all states along a specific path Pao-Ann Hsiung, CSIE, National Chung Cheng University

48. s f f Basic CTL Formulas • M, s |= E X (f) • Exists a next state of s, for which f holds • M, s |= A X (f ) • For all next states of s, fis true s f Pao-Ann Hsiung, CSIE, National Chung Cheng University

49. s f f f Basic CTL Formulas • M, s |= E G (f ) • Exists a path from s, along which f holds in every state • M, s |= A G (f) • For all paths from s, f holds in every state, i.e., globally s f f Pao-Ann Hsiung, CSIE, National Chung Cheng University

50. f f s f Basic CTL Formulas • M, s |= E F (f ) • Exists a path from s, which eventually contains a state in which f holds • M, s |= A F (f) • For all paths from s, eventually there is a state in which f holds s Pao-Ann Hsiung, CSIE, National Chung Cheng University