A New Low Power Flash ADC Using Multiple-Selection Method

1. A New Low Power Flash ADC Using Multiple-SelectionMethod 研 究 生：許庭碩 學 號：98662005 指導教授：陳勛祥 任課教授：易昶霈

2. Referance • Wen-Ta Lee; Po-Hsiang Huang; Yi-Zhen Liao; Yuh-Shyan Hwang;“A New Low Power Flash ADC Using Multiple-Selection Method”Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on20-22 Dec. 2007 Page(s):341 - 344 Digital Object Identifier 10.1109/EDSSC.2007.4450132

3. Outline • Introduction • Traditional flash ADC Architecture • New 4-bit modified flash ADC • A modified low-power 6-bit flash ADC • Simulation and experimental results • Conclusion

4. Introduction • The flash ADC is a frame of A/D converters having very high data conversion speed, low-resolution and large chip area along with large power dissipation.

5. Traditional flash ADC Architecture Comparators:63 Fig. 1. A traditional flash ADC architecture

6. 1.5vref/16 0 0 0 0 0 0 1 0 1 1 0 0 1 1 0 5.5vref/16 8.5vref/16 0 1 1 0 0 0 1 0 0 1 0 0 0 0 0 New 4-bit modified flash ADC 10 Fig. 2. New 4-bitmodified flash ADC

7. Low power comparator Vin>Vre Vout:high Vout!:low Vin<Vre Vout:low Vout!:high Fig. 3. Low power comparator in proposed ADC

8. A modified low-power 6-bit flash ADC Comparators:27 Fig. 4. A modified low-power 6-bit flash ADC

9. 0 0 0 0 0 0 1 A modified low-power 6-bit flash ADC vin=1.5vref/64 Binary code : 000001

10. 0 0 0 0 1 1 0 A modified low-power 6-bit flash ADC Vin=18.5vref/64 Binary code : 010010

11. A modified low-power 6-bit flash ADC

12. The architecture of latch-circuit Fig. 5. The architecture of latch-circuit

13. Simulation and experimental results Fig. 6. The simulation results of 6-bit flash ADC (Vin =0~2 ramp signal) Vin=1 Binary code:100000

14. Conclusion TABLE I TABLE II Comparison results of three different flash ADCs Specifications of proposed flash ADC

15. Thanks