Flash ADC

1. Flash ADC

2. Flash ADC Architecture • Reference ladder consists of 2N equal size resistors • Input is compared to 2N-1 reference voltages • Massive parallelism • Very fast ADC architecture • Throughput = fs • Latency = 1 T = 1/fs • Complexity = 2N

3. Thermometer Code Thermometer code 1-of-n code

4. Flash ADC Challenges • VDD = 1.8 V • 10-bit • VFS = 1 V • DNL < 0.5 LSB • 0.5 mV = 3-5 σ • 1023 comparators • 1 LSB = 1 mV • Vos < 0.5 LSB • σ = 0.1-0.2 mV • 2N-1 very large comparators • Large area, large power consumption • Very sensitive design • Limited to resolutions of 4-8 bits

5. Flash ADC Challenges • DNL < 0.5 LSB • Large VFS relaxes offset tolerance • Small VFS benefits conversion speed (settling, linearity of building blocks)

6. A Typical CMOS Comparator Vos derives from: • Preamp input pair mismatch (Vth,W,L) • PMOS loads and current mirror • Latch mismatch • CI / CF imbalance of M9 • Clock routing • Parasitics

7. Latch Regeneration Exponential regeneration due to positive feedback of M7 and M8

8. Regeneration Speed – Linear Model 

9. Reg. Speed – Linear Model

10. Reg. Speed – Linear Model  x

11. Comparator Metastability Comparator fails to produce valid logic outputs within T/2 when input falls into a region that is sufficiently close to the comparator threshold

12. Comparator Metastability Assuming that the input is uniformly distributed over VFS, then • Cascade preamp stages (typical flash comparator has 2-3 PA stages) • Use pipelined multi-stage latches; PA can be pipelined too • Avoid branching off comparator logic outputs

13. Comparator Metastability Logic levels can be misinterpreted by digital gates (branching off, diff. outputs) – even a wrong decision is better than no decision!

14. CI and CF in Latch • Charge injection and clock feedthrough introduce CM jump in Vo+ and Vo- • Dynamic latches are more susceptible to CI and CF errors

15. Dynamic Offset of Latch Dynamic offset derives from: • Imbalanced CI and CF • Imbalanced load capacitance • Mismatch b/t M7 and M8 • Mismatch b/t M5 and M6 • Clock routing Dynamic offset is usually the dominant offset error in latches

16. Typical CMOS Comparator • Input-referred latch offset gets divided by the gain of PA • Preamp introduces its own offset (mostly static due to Vth, W, and L mismatches) • PA also reduces kickback noise Kickback noise disturbs reference voltages, must settle before next sample

17. Comparator Offset Differential pair mismatch: Total input-referred comparator offset:

18. Matching Properties Suppose parameter P of two rectangular devices has a mismatch error of ΔP. The variance of parameter ΔP b/t the two devices is 1st term dominates for small devices where, W and L are the effective width and length, D is the distance Ref: M. J. M. Pelgrom, et al., “Matching properties of MOS transistors,” IEEE Journal of Solid-State Circuits, vol. 24, pp. 1433-1439, issue 5, 1989.

19. Why Large Devices Match Better? R1 R2 “Spatial averaging”

20. ADC Input Capacitance • N = 6 bits • VFS = 1 V • σ = LSB/4 • AVT0 = 10 mV·μm • 63 comparators • 1 LSB = 16 mV • σ = 4 mV • L = 0.24 μm, W = 26 μm • Small Vos leads to large device sizes, hence large area and power • Large comparator leads to large input capacitance, difficult to drive and difficult to maintain tracking bandwidth

21. Flash ADC Errors

22. Distributed Parallel Processing • SHA-less • Signal and clock propa-gation delay • 2N-1 PAs + latches must be matched • Synchronized strobe signal is critical Going parallel is fast, but also gives rise to inherent problems…

23. Preamp Input Common Mode Input CM difference creates systematic mismatch (offset, gain, Cin, tracking BW, and CMRR) among preamps

24. Sampling Aperture Error • Preamp delay and Vth of sampling switch (M9) are both signal-dependent → signal-dependent sampling point (aperture error) • A major challenge of distributing clock signals across 2N-1 comparators in flash ADC with minimum clock skew (routing, Vth mismatch of M9, etc.)

25. Nonlinear Input Capacitance Signal-dependent input bandwidth (1/RSCin) introduces distortion

26. Input Signal Feedthrough Feedthrough of Vin to the reference ladder through the serial connection of Cgs1 and Cgs2 disturbs the reference voltages

27. Fully-Differential Architecture • VFS doubled • 3-dB gain in SNR • Better CMRR • Noise immunity • Input feedthrough cancelled • Cin nonlinearity partially removed • Effect of Vcmi diff. mitigated

28. Fully-Differential Comparator • Double-balanced, fully-differential preamp • Switches (M7, M8) added to stop input propagation during regeneration • Active pull-up PMOS added to the latch

29. AC-Coupled Preamp • PA input node X sees constant bias throughout all preamps • Autozeroing eliminates PA offsets (stored in C) Ref: A. G. F. Dingwall, “Monolithic expandable 6 bit 20 MHz CMOS/SOS A/D converter,” IEEE Journal of Solid-State Circuits, vol. 14, pp. 926-932, issue 6, 1979.

30. Bubbles (Sparkles) Static/dynamic comparator errors cause bubbles in thermometer code

31. Bubbles (Sparkles) Comparator offset Timing error

32. Bubble-Tolerant Boundary Detector • 3-input NAND • Detect “011” instead of “01” only • “Single” bubble correction • Biased correction Ref: J. G. Peterson, “A monolithic video A/D converter,” IEEE Journal of Solid-State Circuits, vol. 14, pp. 932-937, issue 6, 1979.

33. Built-In Bias Inspecting more neighboring comparator outputs improves performance

34. Majority Voting Ref: C. W. Mangelsdorf, “A 400-MHz input flash converter with error correction,” IEEE Journal of Solid-State Circuits, vol. 25, pp. 184-191, issue 1, 1990.

35. Gray Encoding Only one transition b/t adjacent codes • One comparator output is ONLY used once → No branching! • Gray encoding fails benignly in the presence of bubbles • Codes are also robust over metastability errors

36. Gray Encoding Conversion of Gray code to binary code is quite time-consuming → “quasi” Gray code Ref: Y. Akazawa, et al., “A 400MSPS 8b flash AD conversion LSI,” in IEEE International Solid-State Circuits Conference, Dig. Tech. Papers, 1987, pp. 98-99.