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Half Adder (1-bit)

Half Adder (1-bit). A. B. S. Half Adder. C. A. Sum. B. Carry. Half Adder (1-bit). Full Adder. A. B. S. Full Adder. Carry In (Cin). Cout. Full Adder. AB. Cin. AB. AB. Cin. Cin. Or. A. S. B. Cin. Cout. Full Adder. H.A. H.A. S. A. A. S. A. S. Half Adder.

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Half Adder (1-bit)

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  1. Half Adder (1-bit) A B S Half Adder C

  2. A Sum B Carry Half Adder (1-bit)

  3. Full Adder A B S Full Adder Carry In (Cin) Cout

  4. Full Adder AB Cin AB AB Cin Cin Or

  5. A S B Cin Cout Full Adder H.A. H.A.

  6. S A A S A S Half Adder Half Adder B B C B C Cout Cin Full Adder

  7. A3 B3 A2 B2 A1 B1 A A A A B B B B Full Adder Full Adder Full Adder Full Adder Cin Cin Cin Cin Cout Cout Cout Cout Carry S S S S S3 S2 S1 S A H.A. H.A. B Cout A S Cin B Full Adder Half Adder C 4-bit Ripple Adder using Full Adder A0 B0 S0

  8. Full Adder Propagation Delay A0 B0 Carry Cin S0 1st Stage Critical Path = 3 gate delays = DXOR+DAND+DOR

  9. A1 B1 S1 Full Adder Propagation Delay A0 B0 Cin S0 1st Stage Critical Path = 3 gate delays = DXOR+DAND+DOR 2nd Stage Critical Path = 2 gate delays = DAND+DOR (Since 1st Critical path > DXOR)

  10. Issue of 4-bit Ripple Adder A3 B3 A2 B2 A1 B1 A0 B0 Carry Cin S3 S2 S1 S0 Critical Path = DXOR+4*(DAND+DOR) for 4-bit ripple adder (9 gate levels) For an N-bit ripple adder Critical Path Delay ~ 2(N-1)+3 = (2N+1) Gate delays

  11. Issue of Ripple Adder • Carry propagation is the main issue in an N-bit ripple adder • A faster adder needs to address the serial propagation of the carry bit • Let’s re-examine the equation for full adders

  12. Carry Generate & Propagate Note that all the carry’s are only dependent on input A and B and C

  13. C4 C0 C3 C1 C2 g2 g1 g3 p3 p1 p2 g0 p0 A3 A2 A1 B3 B1 B2 A0 B0 S3 S1 S2 S0 4-bit Carry-Lookahead Adder (CLA) Carry Lookahead Logic

  14. C4 g3 p3 g2 p2 g1 p1 g0 p0 C3 C2 C1 Inefficient Implementation of Carry Lookahead Logic C0 S3 A3 B3 S2 A2 B2 S1 A1 B1 S0 A0 B0 Reuse some gate output results  Little Improvement Carry Delay is 4*DAND + 2*DOR for Carry C4

  15. g3 p3 C3 g2 p2 C2 g1 p1 C1 g0 p0 Implementation of Carry Lookahead Logic Carry Lookahead Logic C0 C4 S3 A3 B3 S2 A2 B2 S1 A1 B1 S0 A0 B0 Only 3 Gate Delay for each Carry Ci = DAND + 2*DOR 4 Gate Delay for each Sum Si = DAND + 2*DOR+ DXOR

  16. D0 P_RECV D1 D2 D3 Detection P_GEN Even Parity Detection 4-bit data Sender Receiver Parity bit (P_GEN) P_RECV = D0  D1  D2  D3 DETECTION = P_GEN  P_RECV DETECTION=1 if P_GEN P_RECV

  17. D3=0 P_GEN=1 D2=1 D1=1 D0=1 Parity Detection Example 4-bit data 0111 Sender Receiver Parity bit (P_GEN) 1

  18. Parity Detection Example Error occur during transmission 4-bit data 0101 Sender Receiver 1 Parity bit (P_GEN) D3=0 P_RECV=0 D2=1 D1=0 D0=1 Detection=1 P_GEN=1

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