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Computer Organization and Design Building a Computer!

Computer Organization and Design Building a Computer!. Montek Singh Mon, Nov 26, 2012 Lecture 16. Building a Computer. A. Instruction. A. B. Memory. D. ALU. 1. 0. THIS IS IT! We are now ready to build a computer. The ingredients are all in place, so let ’ s put them together….

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Computer Organization and Design Building a Computer!

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  1. Computer Organization and DesignBuilding a Computer! Montek Singh Mon, Nov 26, 2012 Lecture 16

  2. Building a Computer A Instruction A B Memory D ALU 1 0 THIS IS IT! • We are now ready to build a computer. • The ingredients are all in place, so let’s put them together… I wonder where this goes? MIPS Kit

  3. Review: The MIPS ISA 5 5 5 5 6 6 16 26 rs rt rd OP 000000 shamt func The MIPS instruction set as seen from a Hardware Perspective R-type: ALU with Register operands Reg[rd]  Reg[rs] op Reg[rt] rs rt immediate 001XXX I-type: ALU with constant operand Reg[rt]  Reg[rs] op SEXT(immediate) • Instruction classes • distinguished by types: • 3-operand ALU • ALU w/immediate • Loads/Stores • Branches • Jumps rs rt immediate 10X011 I-type: Load and Store Reg[rt]  Mem[Reg[rs] + SEXT(immediate)] Mem[Reg[rs] + SEXT(immediate)]  Reg[rt] rs rt immediate 10X011 I-type: Branch Instructions if (Reg[rs] == Reg[rt]) PC  PC + 4 + 4*SEXT(immediate) if (Reg[rs] != Reg[rt]) PC  PC + 4 + 4*SEXT(immediate) 26-bit constant 00001X J-type: jump PC  (PC & 0xf0000000) | 4*(immediate)

  4. Design Approach Our Bag of Components: Registers Muxes + ALU & adders A Instruction A B Memory D ALU WD Data A RA1 RA2 Memory RD 1 0 WA R/W Register Memories File WE (3-port) WD RD1 RD2 “Incremental Featurism” • We will implement circuits for each type of instruction individually, and merge them (using MUXes, etc). Steps: • 1. 3-Operand ALU instrs • 2. ALU w/immediate instrs • 2. Loads & Stores • 3. Jumps & Branches • 4. Exceptions (briefly)

  5. A Few ALU Tweaks Boolean Bidirectional Barrel Shifter Add/Sub 0 1 … • Let’s review the ALU that we built a few lectures ago.(With a few minor additions) A B 5-bit ALUFN Sub Bool Shft Math OP 0 XX 0 1 A+B 1 XX 0 1 A-B X X0 1 1 0 X X1 1 1 1 X 00 1 0 B<<A X 10 1 0 B>>A X 11 1 0 B>>>A X 00 0 0 A & B X 01 0 0 A | B X 10 0 0 A ^ B X 11 0 0 A | B Sub Bool 1 0 Shft Math 1 0 R FlagsV,C N Flag Z Flag

  6. Instruction Fetch/Decode Control Logic CONTROL SIGNALS • Use a counter to FETCH the next instruction: • PROGRAM COUNTER (PC) • use PC as memory address • add 4 to PC, load new value at end of cycle • fetch instruction from memory • use some instruction fields directly (register numbers, 16-bit constant) • use bits <31:26> and <5:0> to generate controls PC 00 Instruction A 32 Memory D +4 32 32 INSTRUCTION WORD FIELDS OP[31:26], FUNC[5:0]

  7. 3-Operand ALU Data Path 00 Instruction A Memory D +4 Rs: <25:21> rs rt rd 000000 Control Logic WERF! 00000 100XXX R-type: ALU with Register operands Reg[rd]  Reg[rs] op Reg[rt] PC Rt: <20:16> RA1 Register RA2 Rd: <15:11> WD WA File WERF RD1 RD2 WE 32 32 A B ALU ALUFN ALUFN WERF 32

  8. Shift Instructions 00 Instruction A Memory D +4 rs rt rd 000000 Control Logic 0 1 shamt 000XXX R-type: ALU with Register operands sll: Reg[rd]  Reg[rt] (shift) shamt sllv: Reg[rd]  Reg[rt] (shift) Reg[rs] PC Rt: <20:16> Rs: <25:21> RA1 Register RA2 Rd: <15:11> WD WA File WERF RD1 RD2 WE shamt:<10:6> ASEL A B ALU ALUFN ASEL! ALUFN WERF 32 ASEL

  9. ALU with Immediate rs rt immediate 001XXX 00 Instruction I-type: ALU with constant operand Reg[rt]  Reg[rs] op SEXT(immediate) A Memory D +4 Rs: <25:21> WERF Rd:<15:11> 0 1 Rt:<20:16> 0 1 1 0 Control Logic shamt:<10:6> ASEL SEXT ALUFN WERF PC Rt: <20:16> BSEL Register RA1 RA2 WD WA WA File RD1 RD2 WE imm: <15:0> SEXT BSEL How do you build SEXT? SEXT A B ALU BSEL! BSEL ALUFN ASEL

  10. Load Instruction 00 Instruction A Memory D +4 Rs: <25:21> Rd:<15:11> WERF 0 1 Rt:<20:16> BSEL 0 1 0 1 Control Logic shamt:<10:6> ASEL BSEL R/W ALUFN ALUFN WERF rs rt 100011 immediate I-type: Load Reg[rt]  Mem[Reg[rs] + SEXT(immediate)] PC Rt: <20:16> BSEL Register RA1 RA2 WD WA WA File RD1 RD2 WE Imm: <15:0> SEXT SEXT SEXT A B ALU Wr WD WDSEL Data Memory Wr Adr RD 32 ASEL 32 0 1 2 WDSEL

  11. Store Instruction 00 Instruction A Memory D +4 Rs: <25:21> WERF Rd:<15:11> 0 1 Rt:<20:16> BSEL 1 0 0 1 SEXT Control Logic SEXT shamt:<10:6> ASEL Wr BSEL WD R/W ALUFN WDSEL Data Memory ALUFN Wr Adr RD WERF 0 1 2 WDSEL rs rt immediate 10X011 I-type: Store Mem[Reg[rs] + SEXT(immediate)]  Reg[rt] PC Rt: <20:16> BSEL Register RA1 RA2 WD WA WA File RD1 RD2 WE Imm: <15:0> 32 No WERF! A B SEXT ALU ASEL

  12. JMP Instructions 00 Instruction A Memory D +4 Rs: <25:21> WERF Rd:<15:11> Rt:<20:16> BSEL 0 1 0 1 SEXT Control Logic SEXT shamt:<10:6> ASEL Wr BSEL WD R/W ALUFN WDSEL WASEL Data Memory ALUFN Wr Adr RD 0 1 2 WDSEL PC<31:29>:J<25:0>:00 26-bit constant 00001X J-type: j: PC  (PC & 0xf0000000) | 4*(immediate) jal: PC  (PC & 0xf0000000) | 4*(immediate); Reg[31]  PC + 4 PCSEL 6 5 4 3 2 1 0 PC Rt: <20:16> WASEL J:<25:0> 0 1 2 Register RA1 RA2 WD 31 WA WA File RD1 RD2 WE Imm: <15:0> PCSEL A B SEXT ALU WERF ASEL PC+4 32

  13. BEQ/BNE Instructions 00 PCSEL 6 5 4 3 2 1 0 Instruction A Memory D +4 Rs: <25:21> WASEL WERF Rd:<15:11> 31 Rt:<20:16> BSEL 1 0 1 0 SEXT Control Logic SEXT shamt:<10:6> ASEL Wr BSEL WD R/W ALUFN WDSEL WASEL Data Memory ALUFN Wr Adr RD 0 1 2 WDSEL PC<31:29>:J<25:0>:00 rs rt 10X011 immediate BT R-type: Branch Instructions if (Reg[rs] == Reg[rt]) PC  PC + 4 + 4*SEXT(immediate) if (Reg[rs] != Reg[rt]) PC  PC + 4 + 4*SEXT(immediate) PC That “x4” unit is trivial. I’ll just wire the input shifted over 2–bit positions. Rt: <20:16> J:<25:0> 0 1 2 Register RA1 RA2 WD WA WA File RD1 RD2 WE Imm: <15:0> Z x4 + Why add, another adder? Couldn’t we reuse the one in the ALU? Nope, it needs to do a subtraction. PCSEL BT A B SEXT ALU Z WERF ASEL PC+4 32

  14. Jump Indirect Instructions 00 PCSEL 6 5 4 3 2 1 0 Instruction A Memory D +4 Rs: <25:21> WASEL WERF Rd:<15:11> rs rt rd 31 000000 Rt:<20:16> BSEL 0 1 1 0 SEXT Control Logic SEXT shamt:<10:6> ASEL Wr BSEL WD R/W ALUFN WDSEL WASEL Data Memory ALUFN Wr Adr RD 0 1 2 WDSEL 00000 00100X PC<31:29>:J<25:0>:00 BT JT R-type: Jump Indirect, Jump and Link Indirect jr: PC  Reg[rs] jalr: PC  Reg[rs], Reg[rd]  PC + 4 PC Rt: <20:16> J:<25:0> 0 1 2 Register RA1 RA2 WD WA WA File RD1 RD2 WE Imm: <15:0> JT Z x4 + PCSEL BT A B SEXT ALU Z WERF ASEL PC+4 32

  15. Loose Ends 00 PCSEL 6 5 4 3 2 1 0 Instruction A Memory D +4 Rs: <25:21> WERF Rd:<15:11> Rt:<20:16> BSEL 0 1 0 1 SEXT Control Logic SEXT shamt:<10:6> ASEL Wr BSEL WD R/W ALUFN WDSEL WASEL Data Memory ALUFN Wr Adr RD 0 1 2 WDSEL rs rt 001XXX immediate PC<31:29>:J<25:0>:00 BT JT I-type: set on less than & set on less than unsigned immediate slti: if (Reg[rs] < SEXT(imm)) Reg[rt]  1; else Reg[rt]  0 sltiu: if (Reg[rs] < SEXT(imm)) Reg[rt]  1; else Reg[rt]  0 PC Rt: <20:16> Reminder: To evaluate (A < B) we first compute A-B and look at the flags. LT = N  V LTU = C WASEL J:<25:0> 0 1 2 Register RA1 RA2 WD WA WA 31 File RD1 RD2 WE Imm: <15:0> JT N V Z C x4 + PCSEL BT A B SEXT ALU N V C Z WERF ASEL PC+4 32

  16. More Loose Ends 00 PCSEL 6 5 4 3 2 1 0 Instruction A Memory D +4 Rs: <25:21> WERF Rd:<15:11> rs rt rd 000000 Rt:<20:16> BSEL 1 0 0 1 SEXT Control Logic SEXT shamt:<10:6> ASEL Wr BSEL WD R/W ALUFN WDSEL WASEL Data Memory ALUFN Wr Adr RD 0 1 2 WDSEL 00000 10101X PC<31:29>:J<25:0>:00 BT JT R-type: set on less than & set on less than unsigned slt: if (Reg[rs] < Reg[rt]) Reg[rd]  1; else Reg[rd]  0 sltu: if (Reg[rs] < Reg[rt]) Reg[rd]  1; else Reg[rd]  0 PC Rt: <20:16> WASEL J:<25:0> 0 1 2 Register RA1 RA2 WD WA WA 31 File RD1 RD2 WE Imm: <15:0> JT N V Z C x4 + PCSEL BT A B SEXT ALU N V C Z WERF ASEL PC+4 32

  17. LUI 00 PCSEL 6 5 4 3 2 1 0 Instruction A Memory D +4 Rs: <25:21> WERF Rd:<15:11> Rt:<20:16> BSEL 1 0 Control Logic Wr BSEL WD R/W ALUFN WDSEL Data Memory ALUFN Wr Adr RD 0 1 2 WDSEL rt 00000 001XXX immediate PC<31:29>:J<25:0>:00 BT JT I-type: Load upper immediate lui: Reg[rt]  Immediate << 16 PC Rt: <20:16> WASEL J:<25:0> 0 1 2 Register RA1 RA2 WD WA WA 31 File RD1 RD2 WE Imm: <15:0> SEXT JT SEXT N V Z C x4 shamt:<10:6> + “16” ASEL 0 1 2 PCSEL BT WASEL A B SEXT ALU N V C Z WERF ASEL PC+4 32

  18. Reset, Interrupts, and Exceptions • Upon reset/reboot: • Need to set PC to where boot code resides in memory • Interrupts/Exceptions: • any event that causes interruption in program flow • FAULTS: e.g., nonexistent opcode, divide-by-zero • TRAPS & system calls: e.g., read-a-character • I/O events: e.g., key pressed • How to handle? • interrupt current running program • invoke exception handler • return to program to continue execution

  19. Exceptions 00 PCSEL 6 5 4 3 2 1 0 Instruction A Memory D +4 Rs: <25:21> WASEL WERF 0 1 2 3 Rd:<15:11> 31 27 Rt:<20:16> BSEL 1 0 Control Logic shamt:<10:6> “16” ASEL 0 1 2 Wr BSEL WD R/W ALUFN WDSEL Data Memory ALUFN Wr Adr RD 0 1 2 WDSEL 0x80000000 Reset: PC  0x80000000 PC<31:29>:J<25:0>:00 0x80000040 BT 0x80000080 JT Bad Opcode: Reg[27]  PC+4; PC  0x80000040 IRQ: Reg[27]  PC+4; PC  0x80000080 PC Rt: <20:16> J:<25:0> Register RA1 RA2 WD WA WA File RD1 RD2 WE Imm: <15:0> RESET SEXT JT SEXT N V Z C IRQ x4 + PCSEL BT WASEL A B SEXT ALU N V C Z WERF ASEL LSEL PC+4 32

  20. MIPS: Our Final Version 0x80000000 PC<31:29>:J<25:0>:00 0x80000040 0x80000080 JT BT 00 PCSEL 6 5 4 3 2 1 0 Instruction A Memory PC D +4 Rs: <25:21> Rt: <20:16> WASEL J:<25:0> 0 1 2 3 Rd:<15:11> Register RA1 RA2 31 WD WA WA File 27 Rt:<20:16> WERF RD1 RD2 WE Imm: <15:0> RESET BSEL 1 0 SEXT SEXT Control Logic JT N V Z C IRQ shamt:<10:6> “16” ASEL 0 1 2 PCSEL BSEL WDSEL WASEL Data Memory A B ALUFN SEXT ALU Wr Wr WD R/W ALUFN RD N V C Z Adr WERF ASEL 0 1 2 WDSEL PC+4 This is a complete 32-bit processor. Although designed in “one” class lecture,it executes the majority of theMIPS R2000 instruction set. Executes one instruction per clock All that’s left is the controllogic design x4 + BT

  21. MIPS Control The control unit can be built as a large ROM Problem Set #5!

  22. Summary • We have designed a full “miniMIPS” processor! • has datapath, which includes registers, ALU • instruction and data memories • control unit governs everything! • Next couple of classes: some advanced topics • memory hierarchy: caches etc. • pipelining the processor: benefits and challenges • wrap up (grades etc.) • Don’t forget: Problem Set #5 and Quiz #4

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