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FVTX LL1

FVTX LL1. What should an FVTX LL1 do? Goals of an FVTX LL1 Relationship to the Forward Muon Trigger Upgrade The Forward Muon Trigger Upgrade Basic Design Simulation pp Rejection (W physics) HI Rejection (Inv. Mass Trigger) Adding the FVTX LL1 FVTX LL1 Algorithm Hardware

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FVTX LL1

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  1. FVTX LL1 • What should an FVTX LL1 do? • Goals of an FVTX LL1 • Relationship to the Forward Muon Trigger Upgrade • The Forward Muon Trigger Upgrade • Basic Design • Simulation • pp Rejection (W physics) • HI Rejection (Inv. Mass Trigger) • Adding the FVTX LL1 • FVTX LL1 Algorithm • Hardware • Simulations Required… J. Lajoie - FVTX LL1 Collaboration Mtg.

  2. MuID LL1 Rejections • Heavy flavor physics in the muon arms currently limited by the MuID LL1: Single Muon Physics (from the proposal) Dimuon Physics (from the proposal) NEED J. Lajoie - FVTX LL1 Collaboration Mtg.

  3. What can the FVTX LL1 add? • An FVTX LL1 can contribute to three main types of triggers: • Event trigger for Min-Bias and Ultraperipheral physics • Displaced single tracks for open charm and beauty • Pair trigger for J/Y, B -> J/Y and upsilon production • The FVTX LL1 can’t do it alone • You need the muon arm to select muons for the latter two triggers • There’s no way you’ll get the needed rejection otherwise • Need momentum selectivity • Existing MuID LL1 extremely sensitive to beam backgrounds. J. Lajoie - FVTX LL1 Collaboration Mtg.

  4. Forward Muon Trigger Upgrade J. Lajoie - FVTX LL1 Collaboration Mtg.

  5. Trigger Rate and Rejection (W Physics) REAL DATA Design Luminosity √s = 500 GeV σ=60mb L = 2x1032/cm2/s m momentum dist. At vs=200 GeV PT>10GeV/c HQ signal Total X-sec rate＝12MHz PT>20GeV/c W signal DAQ LIMIT =1-2kHz （forμarm） 25 50 Required RF ~ 10,000 Momentum GeV/c Need Momentum Selectivity in the LVL-1 Trigger! J. Lajoie - FVTX LL1 Collaboration Mtg.

  6. RPC1(a+b) MuTr St. 1 RPC2 Trigger Algorithm Candidates found by matching RPC1/2 hits within angular range. Momentum cut made by matching hit in MuTr station 2 within three cathode strip2 of RPC projection. (MuID LL1 1D Trigger also required.) (RPC3 hit also required in three inner theta rings) J. Lajoie - FVTX LL1 Collaboration Mtg.

  7. Detector Setup – Run 10 J. Lajoie - FVTX LL1 Collaboration Mtg.

  8. Detector Setup – Run 12 J. Lajoie - FVTX LL1 Collaboration Mtg.

  9. Simulation Framework • Framework designed to permit integrated trigger studies with new upgrade detectors • Steering routine “ForwardTriggerSim.C” • Additional objects for each trigger system • MuID LL1 • Same hardware simulator used in online monitoring (Mutoo input added) • MuTrRPC LL1 • Combined MuTr+RPC LL1 trigger algorithm • MuTrLL1 • Based on Aoki’s code • NCC LL1 • Basic algorithms for 2x2, 4x4 and flying 8x8 in place • FVTX LL1 • Under development… • All code in CVS • Look in offline/analysis/MuonTriggerUpgradeSim J. Lajoie - FVTX LL1 Collaboration Mtg.

  10. pp Minbias Events @ 500 GeV • Regenerated pythia pp minbias events at ISU • 997,000 events generated in total • Minbias pythia configuration • Run through pisa including all forward detectors: • BBC, MuID, MuTr, NCC, MuRPC’s, FVTX • Converted to DST’s for analysis • 1,000 events per DST • All DST’s stored locally at ISU • Quick access to events • Run through full event sample in ~2hrs J. Lajoie - FVTX LL1 Collaboration Mtg.

  11. “Baseline” Rejections/Efficiency • Based on 997,000 pythia pp events @500GeV. • Rejection factors are combined for both muon arms. • Additional rejection possible with small loss in efficiency J. Lajoie - FVTX LL1 Collaboration Mtg.

  12. 10,000 Rejection vs. RPC Noise Rate Error bars on rejection are statistical only. No MuTr St2 noise included North Arm South Arm Both Arms J. Lajoie - FVTX LL1 Collaboration Mtg.

  13. HI Triggering • Can the same trigger be extended to be useful as a J/Y trigger at RHIC-II? • Widen the MuTr ST2 Dstrip cut • Select lower momentum muons • Sort candidates by sign of charge • Use sign of Dstrip • Use correlation between pZ and Dstrip • Lookup table to generate pZ • Theta/phi at RPC2 to get pX, pY • Combine opposite sign candidates to get invariant mass • Breaks the octant boundary! • Can we do this in hardware? • Set invariant mass windows for triggering J. Lajoie - FVTX LL1 Collaboration Mtg.

  14. Invariant Mass (GeV/c2) Invariant Mass (GeV/c2) Single J/Y events • Efficiency ~60% in each arm • Dominated by same octant requirement (~80% without) Invariant mass resolution ~600MeV J. Lajoie - FVTX LL1 Collaboration Mtg.

  15. Rejection via HIJING • Trigger rejection estimated using HIJING/double-HIJING events • Mass window 2.2 to 4 GeV (2.2 to 4.2 GeV) J. Lajoie - FVTX LL1 Collaboration Mtg.

  16. Relative Yield Invariant Mass (GeV/c2) Invariant Mass Background (from Double-HIJING Events) North South Upsilon trigger? J. Lajoie - FVTX LL1 Collaboration Mtg.

  17. MuID LL1 Symset Matching • Improve trigger rejection by explicit matching to hit MuID LL1 symsets • Will require redesign/implementation of existing MuID LL1 trigger (Could also be implemented with a 1D1S seed trigger) J. Lajoie - FVTX LL1 Collaboration Mtg.

  18. MuTr LL1 Channel Count Channel Counts: Fibers will come off the detector at 1.25Gbit (96 bits) and combined to 2.5 Gbit fibers (192 bits). Fiber Counts (@ 2.5Gbit) : NOTE: MuTr clustering to be done at FEM level. J. Lajoie - FVTX LL1 Collaboration Mtg.

  19. RPC LL1 Channel Count RPC channel counts assume channels OR’d in pairs of rings at FEM level, highest channel count in pair used. Channel Counts: Assume RPC1a and RPC1b OR performed at FEM level: Fiber Counts (@ 2.5Gbit) : J. Lajoie - FVTX LL1 Collaboration Mtg.

  20. 12 fibers per octant maximum 12 x 2.5Gbit serial lines available (RPC1,2,3 @ 2.5Gbit) xcvr P1 xcvr Virtex-4 FX20/40 VME Logic xcvr xcvr P0 xcvr 1 x 2Gbit serial line (Aurora protocol) xcvr 32 bits LA/LD, clock control (MuTr St2 @ 2.5Gbit) xcvr P2 xcvr Virtex-4 FX20/40 xcvr (MuTr St1 @ 2.5Gbit) xcvr xcvr (MuTr St3 @ 2.5Gbit) xcvr Virtex-4 Event Readout (4 daughtercards total) P3 (One board is 4 octants.) (9 fibers per octant) J. Lajoie - FVTX LL1 Collaboration Mtg.

  21. LL1 Board Layout 70mm x 250mm Fiber Receivers J. Lajoie - FVTX LL1 Collaboration Mtg.

  22. Optical Connect • Using new high-density optical (receive only) connections • Agilent AFBR 732/742 series (12 inputs) • 2.5Gb/s on each input J. Lajoie - FVTX LL1 Collaboration Mtg.

  23. Level-1 Electronics Development • Redeveloped VME Interface • Existing interface logic (Cypress 960/4) EOL • Option to use commercial FPGA core replacement custom ASICS developed for military applications • Decided to purchase FPGA core ($6K) • Millogic 960/964 cores implemented, debugged and tested on Xilinx prototyping board wired in to VME crate, including multi-chip capabilities. • Exploring Xilinx Virtex-4/5 • Integrated multi-Gbit serial interfaces • Eliminates need for interface logic, complicated/dense bus • Simplifies inter-chip communication • This is a departure from just revising the MuID LL1 board design • Current design doesn’t scale well with new technologies • Some existing problems extremely difficult to solve • Bus termination J. Lajoie - FVTX LL1 Collaboration Mtg.

  24. Development and Schedule • Plan to pursue through Spring/Summer: • Virtex-4/5 development and testing • Purchased development board w/Cu and XCVR interfaces • “Loopback” serial connections for chip-to-chip comm. development • Use this as a platform to develop/test FPGA code for final board • Produce/populate a prototype board (Summer 2007) • Simple design, attention to serial link traces • Take advantage of learning cycle from development • Build the final hardware as late as possible in the development cycle • Schedule • Prototype LL1’s : Summer 2007 • LL1 Design Review : November 2007 • LL1 Production: Spring 2008 J. Lajoie - FVTX LL1 Collaboration Mtg.

  25. Adding the FVTX LL1… J. Lajoie - FVTX LL1 Collaboration Mtg.

  26. FVTX LL1 Revisited r • What will the FVTX LL1 have to do: • Determine the event vertex • Combine hits with linear correlation coefficient ~1 • For a solenoidal field a fit to tracks in r,z is a straight line • Track list contains slope, intercept for fit, z(r=0) • Histogram z(r=0) for each track • Better yet, intersect pairs of lines (nonzero r for beam spot) • Correlation coefficient calculation could be integer • Octant-by-octant? Or can each octant determine its own vertex? • Needs to be studied in simulation • Answer likely different for p+p, Au+Au • Histogram determines event vertex • Sort track list for displaced vertices • Calculate r(zVTX) for all tracks • Floating point or integer? z B J. Lajoie - FVTX LL1 Collaboration Mtg.

  27. Linear Correl. Coefficient 200<pT<400 MeV Quick check – MC hits in FVTX from same MC track ID, sorted by pT (AuAu Hijing events) r=1 – straight line 400<pT<600 MeV 600<pT<800 MeV J. Lajoie - FVTX LL1 Collaboration Mtg.

  28. Displaced Vertices • Want tight DrLOWER • Consistent with resolution, keep most charm/beauty decays • Momentum dependent? • Want tight DrUPPER • Consistent with ct~300-500um • Eliminate pion decays • Again, should this be momentum dependent? J. Lajoie - FVTX LL1 Collaboration Mtg.

  29. Track Matching • Match tracks in the FVTX and Muon Forward Trigger using hit locations in the last plane of the FVTX and the inner plane of the Muon Forward Trigger (MuTr ST1 or RPC1a,b) Momentum Ranges theta theta phi phi FVTX LL1 Muon Forward LL1 J. Lajoie - FVTX LL1 Collaboration Mtg.

  30. FVTX LL1 Hardware • Can we utilize the hardware being developed for the Muon Forward Upgrade for the FVTX LL1? • STTR hardware development will use the daughtercard format • 10 Fibers/ROC (one wedge) • What’s the low momentum cutoff if we track in one wedge? • Can we pack more data into faster fibers? • FPGA daughtercard can contain: • Two high-density FPGA’s • Embedded PPC’s a plus for this application • High-speed memory (several GB) • Like to try a prototype of the daughtercard design with the LDRD • Proof-of-principle of a lot of key concepts J. Lajoie - FVTX LL1 Collaboration Mtg.

  31. Simulations… • Lots of simulation work needs to be done: • Establish vertex finding algorithm • Study pT cutoff and efficiency as a function of slice width • Study sharing of vertex information • Do all slices need to share vertex information? • Study displaced vertex cuts • Should DrUPPER, DrLOWER be a function of momentum? • Do we win with this or does the addedd complication hurt? • Study track matching with Muon Forward Trigger • What momentum windows are required • Combine with Muon Forward Trigger • Study single, dimuon triggers • Efficiency and rejection in p+p, Au+Au… J. Lajoie - FVTX LL1 Collaboration Mtg.

  32. BACKUP J. Lajoie - FVTX LL1 Collaboration Mtg.

  33. MuTR LL1 Simulations • I took a copy of Aoki’s code and created a module that hooks into the forward simulation framework • It’s greatly modified, so mistakes are mine, not Aoki’s • Run algorithm on same events, only parameter is Dstrip cut • Resolution, etc., is set by MUTOO response chain Strips at Station 2 Strips at Station 3 Strips at Station 1 Cathode clustering, uses peak strip accept Dstrip :Sagitta at station 2 Dstrip<=1 J. Lajoie - FVTX LL1 Collaboration Mtg.

  34. MuTr LL1 Rejections MuIDLL1 required to fire, no geom. match Rejection factors combined for both arms Comparable to Aoki’s results from Aug. 2005 meetting. (uses PEAKSTRIP not CENTERSTRIP) J. Lajoie - FVTX LL1 Collaboration Mtg.

  35. RPC2 RPC3 RPC1a Cluster Size (in number of RPC strips) RPC Clusters • RPC cluster size using data from Colorado • Implemented cluster width using fit by Andy Glenn • MC yields good fit to observed cluster size distribution • Fit test bench data assuming a hit-inducing Gaussian radius • Extendible to arbitrary pad sizes. J. Lajoie - FVTX LL1 Collaboration Mtg.

  36. Fiber Data Rates • Data rate on fibers assumes 8b/10b encoding, 16-bit words, two header words (frame header and clock counter) • The data rate on the fiber is then given by: • N is number of data frames Nominal 2.5Gbit fiber. J. Lajoie - FVTX LL1 Collaboration Mtg.

  37. Logic Estimate • Assume the logic required scales like the number of input bits, scale MuID LL1 logic required: • 1920 bits for MuID LL1, processed in five XCV2000E chips • 38,400 logic cells • At best 21% utilization • 1248 bits for MuTr+RPC LL1, to be processed in one chip • Assume we can go to 50% occupancy • Require 38,400*5*(1248/1920)*(21/50) = 52,416 logic cells • Possible Xilinx Options: • Virtex-4: • XC4VFX60 (12 Rocket I/O, 56,880 logic cells) • XC4VFX100 (16 Rocket I/O, 94,896 logic cells) • Virtex-5: • XC5VLX85T (12 Rocket I/O, 82,944 logic cells) • XC5VLX110T (16 Rocket I/O, 110,592 logic cells) J. Lajoie - FVTX LL1 Collaboration Mtg.

  38. Hi-Tech PCIE-SYS60 PCIe Module with multiple hardware and RocketIO Serial connections. Uses SFP Optical Modules (Finisar) Loopback connection using these two transceivers – allows testing of RocketIO MGT’s. J. Lajoie - FVTX LL1 Collaboration Mtg.

  39. Rocket I/O + Chipscope Frame errors – 125MHz clock too slow (156Mhz min). J. Lajoie - FVTX LL1 Collaboration Mtg.

  40. RPC dimensions all units in mm (except theta) J. Lajoie - FVTX LL1 Collaboration Mtg. strip length and width consider full acceptance in theta and phi in the octants (i.e. no loss due to readout and boxes)strip widths are determined at the outer radius of two paired rings

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