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FVTX Trigger Timing Study

FVTX Trigger Timing Study. GL1 Active Width. As a result of the GL1 input phase scan, the plateau width is measured where accepts 100% input pulse. The active region varies depending on the input pulse width. Input Pulse Width=110ns. March 5 th , 2015. Working point 53.53 3/5/2015 ~.

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FVTX Trigger Timing Study

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  1. FVTX Trigger Timing Study

  2. GL1 Active Width As a result of the GL1 input phase scan, the plateau width is measured where accepts 100% input pulse. The active region varies depending on the input pulse width.

  3. Input Pulse Width=110ns March 5th, 2015 Working point 53.53 3/5/2015 ~ Efficiency = Visual Scaler before GL1 input/GL1 rates 72.6ns There was 1/8th BCLK shift between the measurements Blue an Orange dots .

  4. Input Width=110ns March 5th, 2015 Working point 53.78 3/5/2015 ~ 96ns Phase is 110ns wider.

  5. Phase Scan 1 (South) March 5th, 2015 GL1 rates [Hz] 50ns Input Pulse Width=50ns

  6. Phase Scan 2 (North) 40ns Input Pulse Width=80ns

  7. Phase Scan 3 (North) <10ns Input Pulse Width=50ns

  8. Case 1 : Should issue trigger BCLK Input TTL  GL1 Trigger Latch timing

  9. Case 3 : shouldn’t issue trigger BCLK Input TTL × GL1 Trigger

  10. Case 1 : Should issue trigger BCLK Input TTL  GL1 Trigger

  11. Default Time difference South North No custom delay between North and South. The difference was 40ns when this was measured. However, the timing can be shifted ± 1/8th BCLK.

  12. After optimized timing March 5, 2015 North South

  13. Trigger Timing at GL1 input North South MPC 4x4c April 12, 2015

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