Labs Practicing in Design of Combinational Networks and FSM with Concurrent Error Detection

1. 2075Microprocessor systems Labs Practicing in Design of Combinational Networks and FSM with Concurrent Error Detection Tatjana Stanković, Goran Djordjević, Mile Stojčev

2. Outline of the talk I. Introduction II. Review of the Exercises III. Tutorial Content IV. Description of Overall Design Procedure V. Examples of VHDL synthesis VI. Concurrent error detection VII. Conclusion

3. 2075Microprocessor systems • Directions: • Electronics, • Communications, • Microelectronics • VII semester 2+2+1 • VIII semester 2+2+1

4. Outline of the talk I. Introduction II. Review of the Exercises III. Tutorial Content IV. Description of Overall Design Procedure V. Examples of VHDL synthesis VI. Concurrent error detection VII. Conclusion

5. 2075Microprocessor systems Structure of Lab Exercises Lab exercises Programming oriented Logic design oriented DOS (4 exercises) VHDL description of three stage pipelined system Intel 80x86 (15 exercises) Four more exercises about VHDL design of logic structure with concurrent error detection MIPS (5 exercises)

6. 2075Microprocessor systems What we propose? Involving four additional exercises in logic design to cover the following topics: • CAD tools for logic design • Design of combinational networks with concurrent error detection with examples • Design of sequentional networks with concurrent error detection with examples

7. 2075Microprocessor systems What kind of literature use students? • Tutorial for VHDL design • Textbook for Digital Logic Design

8. 2075Microprocessor systems Outline of the talk I. Introduction II. Review of the Exercises III. Tutorial Content IV. Description of Overall Design Procedure V. Examples of VHDL synthesis VI. Concurrent error detection VII. Conclusion

9. 2075Microprocessor systems Tutorial Content • General Introduction • VHDL for Synthesis After passing this step students become familiar with writing and simulating VHDL code, modeling combinational and sequential circuits, using design hierarchy. • CAD tools and Design Flow During this step students learn how to use CAD tool for designing logic structures with PLD circuits.

10. 2075Microprocessor systems Outline of the talk I. Introduction II. Review of the Exercises III. Tutorial Content IV. Description of Overall Design Procedure V. Examples of VHDL synthesis VI. Concurrent error detection VII. Conclusion

11. 2075Microprocessor systems Description of the Overall Design Procedure • Design entry • Design synthesis • Functional simulation • Design implementation

12. CAD system Xilinx Integrated Software Environment - ISE 5 for design entry, synthesis and physical implementation for FPGA circuits ModelSim XE II/Starter 5.7 for functional and timing VHDL simulation.

13. Design flow ModelSim ISE

14. Design entry - writing source code in VHDL - behavioral description

15. Design synthesis Synthesis Report Synthesis is process of generating a logic circuit from a formal circuit description, automatically. This process translate, or compile, VHDL code into a network of logic gates.

16. Functional simulation Test bench Simulation output

17. Design implementation Post-Place & Route Static Timing Report Floor Planner

18. 2075Microprocessor systems Outline of the talk I. Introduction II. Review of the Exercises III. Tutorial Content IV. Description of Overall Design Procedure V. Examples of VHDL synthesis VI. Concurrent error detection VII. Conclusion

19. VHDL synthesis of combinational circuits Four ways to describe a MUX– behavioral description If-then-else statement select statement case statement conditional assignment

20. Arithmetic circuits Ripple-carry adder – structural description

21. VHDL synthesis of sequential circuitsFSM code template - layout combinational next state and output logic The correct model is one in which the sequential current state logic has been separate from the combinational next state and output logic. sequential current state logic

22. VHDL synthesis of sequential circuitsFSM state encoding Source code using sequential state encoding: Coding schemes (sequential, Gray, Johnson, and one-hot) are defined in separate package:

23. 2075Microprocessor systems Outline of the talk I. Introduction II. Review of the Exercises III. Tutorial Content IV. Description of Overall Design Procedure V. Examples of VHDL synthesis VI. Concurrent error detection VII. Conclusion

24. Concurrent error detectionWhy it is important? Technological advances have increased drastically the complexity of integrated circuits that can be realized on a single chip. The move towards VLSI technologies with higher frequencies, lower voltage levels, and smaller noise margins is increasing the susceptibility of systems to transient and intermittent faults. Early detection of errors is crucial for preserving the state of the system and maintaining data integrity. Techniques for concurrent error detection (CED) permit early detection and containment of errors before they can propagate to other parts of the system and corrupt data.

25. General structure of CED One general approach for CED is to encode the outputs of a circuit with an error detecting code.

26. The insertion of CED circuitry We use a methodology for insertion of CED in synthesizable VHDL description of the original circuit, at the front-end of the synthesis process. This methodology has several advantages: • It allows the error detection circuitry to be optimized along with the functional circuitry. • The CED circuitry is taken into account when satisfying timing constraints. • The approach of inserting the CED circuitry can be easily and seamlessly incorporated into the standard design flow.

27. Techniques for CED The techniques for CED depend on the way in which the output of functional logic is encoded. We use: • duplication function • parity codes • Berger codes • Bose-Lin codes All mentioned techniques can be applied on the outputs of the combinational circuits or on the states of sequential circuit.

28. Duplication of function as a technique for CED The design implements two copies of the same circuit. The second copy produces output values complementing the value of the first copy, and a tree of two-rail code (TRC) checkers makes a bitwise comparison of the outputs.

29. Parity codes as a technique for CED The parity bit is equal to the sum modulo 2 of the information bits or their complements. A parity check code is a code in which each check bit is a parity check for a group of output bits.

30. Berger and Bose-Lin codes as a technique for CED The Berger check symbol of the information can adopt either the binary representation of the number of zeros in the information (B0) or the ones complement of the number of ones in the information (B1). Bose-Lin codes - similar to Berger codes, but the number of bits is performed modulo 2, 4, 8 etc.

31. Layout of Lab Exercise for Combinational Networks with CED Original circuit Check symbol generator Check symbol generator is described as a separate process which include: - VHDL code of the original circuit - Code that transforms circuit outputs into check symbol bits

32. Layout of Lab Exercise for Combinational Networks with CED Checker Structural description of circuit with CED hardware

33. FSM with CED Parity bits technique The simplest technique for inserting CED in FSM is to append a parity bit to each state-codeword.

34. Conclusion Extension of Lab exercises for course Microprocessor Systems is considered with goal to include VHDL synthesis of combinational and sequential networks with concurrent error detection using contemporary CAD tools.