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Tracker DAQ Update

Tracker DAQ Update. DFPGA/AFPGA Update VLSB Firmware Progress Plans/Schedule. Terry Hart, Tracker Phone Meeting, April 26, 2007. DFPGA/AFPGA Update. Senerath, Bill, and I have clarified the protocol for data transfers on the bidirectional bus between the DFPGA and AFPGA.

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Tracker DAQ Update

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  1. Tracker DAQ Update • DFPGA/AFPGA Update • VLSB Firmware Progress • Plans/Schedule Terry Hart, Tracker Phone Meeting, April 26, 2007

  2. DFPGA/AFPGA Update • Senerath, Bill, and I have clarified the protocol for data transfers on the bidirectional bus between the DFPGA and AFPGA. • We expect to have the firmware roughed out in about two weeks. • After that, we will concentrate on testing AFE IIt operation at different frequencies. Terry Hart, Tracker Phone Meeting, April 26, 2007

  3. VLSB Update • I’ve met with Bill Haynes and Neal Wilcer from FNAL Computing Division to clarify some questions we had about VLSB firmware and proposed modificatons. • Upcoming plans • Bill and Neal will work on fast clear of memory banks after spill is done. • We will work on getting block transfers to work on AFE IIt test stand. • After that, work on “squeezing out null words” will become main VLSB priority. Terry Hart, Tracker Phone Meeting, April 26, 2007

  4. Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec TriP-t/ADC Control Firmware Hardware tests DFPGA/AFPGA I/O Bus Board test at 53.104 MHz Board test at 55 MHz Simulations at different frequencies Data transfer protocol AFPGA Firmware Write firmware controlling bitmap transfers Test pipeline/buffer operation Test mode development DFPGA Firmware Make 4-level trigger buffer Data format Event aggregation VLSB Firmware Data block transfer Fast clear of memory banks Suppress writing zeros to memory Done Done Done Terry Hart, Tracker Phone Meeting, April 26, 2007

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