1 / 16

Exercise Assistant

Exercise Assistant. EE330 Lab Final Project Curtis Mayberry and Josh Sevcik. Project Overview. Create an exercise assistant that will take in an Ascii user input describing the user and the user’s current heart rate and then will return to the user useful exercise information.

devin
Download Presentation

Exercise Assistant

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Exercise Assistant EE330 Lab Final Project Curtis Mayberry and Josh Sevcik

  2. Project Overview • Create an exercise assistant that will take in an Ascii user input describing the user and the user’s current heart rate and then will return to the user useful exercise information. • This Exercise information includes the total Calories burned for the day, current Calorie balance, time remaining until the desired calorie deficit at current pace, and a warning light that warns the user if their heart rate is too high.

  3. Assumptions • 5 digit Ascii input available in parallel • Input limits • Age < 127 years • Weight < 511 kg • V0_max < 255 • Calories: up to 9999 input • Desired deficit: up to 9999 input • Exercise assistant should not be used for much longer than 24 hours

  4. General module layout

  5. Original module layout

  6. Input plan • Any input that is not a number is ignored • First number of five number input specifies the input to be changed • This allows any input to be changed at any time • 0: Age • 2: Weight • 3: V0_max • 4: Calories • 5: Desired Deficit • 6: Reset

  7. 7-segment output • 3 separate seven segment displays • 4 digits a piece • 32 pin output to seven segment displays

  8. Code example for Ascii Converter always @(posedgeclk)begin if(reset) begin age = 20; weight = 135; sex = 0; v0_max = 40; Calories = 2000;desired_deficit = 100; end else if ((ascIn[34:32]==3'b011) && (ascIn[27:25]==3'b011) && (ascIn[20:18]==3'b011) && (ascIn[13:11]==3'b011) && (ascIn[6:4]==3'b011)) begin //convert first decimal number(least significant) case(ascIn[3:0]) 4'b0000: bOut0 = 0;

  9. Layout Sample: Ascii Converter

  10. Schematic Sample: Ascii Converter

  11. Further Notes

  12. Consider This… • always @(posedgeclk or posedgecalc_reset) • begin • if(calc_reset) • begin • Exp <= 0; • cycles <=0; • EE <= 0; • bal <= 0; • tr <= 0; • end • else • begin • //estimator module • EE <= ((-593954)+sex*((-363781)+2710*age+3940*weight+4040*v0_max+6340*heart) + (1-sex)*(2740*age+1030*weight+3800*v0_max+4500*heart))/41840; • //Days_Exp module • cycles<=cycles+1; • //Exp=cycles; • Exp<=((cycles*EE)/360); • //balance module • bal <= Calories - Exp; • //time_remaining module • tr<=(desired_def - Exp)/EE; • end • end

  13. Successes • All DRC checks passed • All modules work: Simulations successful • All circuits synthesized in RTL • All circuits imported to Cadence

  14. Weaknesses • LVS ran, but not completely successful • Problems with pins needing renamed and • 5-digit ascii parallel load may require extra circuitry ( can be accommodated in another module or in input device) • Separate module had trouble instantiating into one main module (net-list error attributed to Library issues) • Biggest mistake: Breaking it up into too many pieces, the project was overestimated- • 8 was too many, but 3 was the correct number • Made sense at beginning but as we became more comfortable with Verilog, coding larger modules became easier

  15. Bringing it all together • //converted inputswire [13:0] age, weight, sex, v0_max, Calories, desired_deficit, heart_converted;wire [13:0] EE; //Estimated Expenditure (output of estimator)wire [13:0] Exp; //Day's Expenditure (output of estimator)wire [13:0] bal; //balance (goes to 7 segment converter modulewire [13:0] tr;output [32:0] caloriesdisplay, balancedisplay, trmaindisplay;output warning;//sub-circuitsascii_decodeascii_converter_inst(ascii_input, reset_ascii_conv, age, weight, sex, v0_max, Calories, desired_deficit, clk);heartrateconverterheartconv_inst(heart, clk, heart_converted);estimator estimator_inst(clk, age, weight, sex, v0_max, heart_converted, EE);heartwarningheartwarning_inst(age, heart_converted, warning, clk);Days_ExpDays_Exp_inst(EE,Exp,clk);balance balance_inst(desired_deficit, bal, Exp, clk);time_remainingtime_remaining_inst(bal, EE, tr, clk);seg4 seg4_inst(clk, Calories, bal,tr,caloriesdisplay,balancedisplay,trmaindisplay);

  16. Questions? • Learned a lot of Verilog • Learned how to write Verilog to ensure synthesis and LVS • Learned a lot about design planning and design considerations

More Related