Understanding Semiconductor Manufacturing Processes and Band Structure

1. FEOL Front End Of Line

2. Background • Process steps up to ‘creating the transistors’ in the manufacturing Line==> Front End Of Line ==> FEOL • Connecting the Transistors, capacitors etc ==> BEOL • Semiconductor • Band Structure, current carriers, mobility, bias • MOS device basics • structure, Operation, depletion, inversion, pinch off • Issues • Steps in manufacturing

3. FEOL: Device - - N P N + + Forward Bias - + N P N - + Reverse Bias BiPolar Device- Schematic N P N Emitter Base Collector

4. Gate (Base) Gate Dielectric (oxide) Source (Emitter) Drain (Collector) Electric Field of gate FEOL: FET Device - Simplified Schematic P N-Well P P PMOS NMOS is similar (swap P and N)

5. Background: Electron Bands • Electrons in an atom can hold only certain energy levels (allowed levels, quantized energy levels) • Solution of Schroedinger’s equation • When two identical atoms come close (eg. Silicon and silicon), electron levels split • Pauli’s exclusion principle for fermions • almost always valid (*neutron stars, black holes) • When many atoms come together, allowed energy levels form “bands” • Electrons temporal/spatial position given by wave function (uncertainty principle)

6. 1 Atom N Atom Allowed Energy Levels Allowed Energy Levels Background: Bands • When many atoms come together, the energy bands form

7. Background: Bands • Energy bands and gaps depend on space between the atoms Energy Space between atoms

8. Background: Solid groups • Solids: • Ionic bond, covalent bond, metallic bond • insulator, metal, semiconductor • Resistivity • insulator: > 1Mohm-cm • conductor: < 10 uohm-cm • at room temperature

9. Background: Band gap • Energy bands and gaps depend on space between the atoms METAL INSULATOR Filled levels Empty levels Energy BAND GAP Space between atoms Space between atoms

10. Background: Bandgap • Semi conductors similar to insulators with small band gap ( 1eV) (Insulators > 3eV) • Valence band : Top most occupied band • Conduction band: lowest empty band • Valence and conduction bands overlap: Metal • Band gap: DE between top of valence band and bottom of conduction band • Metals: Band overlap

11. Background: Resistance vs Temp • Indirect and Direct Band Gap • Silicon - indirect, GaAs- Direct band gap • phonon assisted jump (momentum, energy) • Resistance vs Temp • phonon scattering: metal: • electron in conduction bands/ holes in valence bands: semiconductor

12. Background: Semiconductors • Silicon is “intrinsic” semiconductor • Addition of other ‘contaminant’ (Dopant) to alter its conductivity : Extrinsic • N Type (negative) or P Type (positive) • Donor electron, Acceptor hole (larger effective mass) • Phosphorous for N Type, Boron for P Type (for example) • Overall neutrality is maintained (number of protons = number of electrons) • Counter doping (when some P and some N type materials are added) • (junction is where N = P)

13. Background: Conduction • For intrinsic semiconductors (based on calculations) • EF - Fermi level. Energy where the prob(electron) = 0.5 • = half way between EC and EV for semiconductor • For intrinsic case, n = p

14. N Atom Allowed Energy Levels N Doping P Doping Dopant Valence Band Background: Doping Conduction EF Valence • Doping shifts Fermi level, smaller “band gap” • Extrinsic Semiconductor : “n” not equal to “p”

15. Background: Doping • Majority carrier, Minority carrier • Carrier Mobility • hole has heavier (effective) mass • less mobile • P-N junction • depletion region PN junction N Type P Type EC EF EF EF EV N P

16. Background: Doping and Solid Groups Conductivity (Ohm-CM) -1 Copper Silver Gold 108 106 Aluminum Metals 104 Bismuth 102 1 Germanium 10-2 Semi conductors Silicon 10-4 Boron 10-6 Glass 10-8 PVC Insulators Phosphorus 10-12 10-14 Teflon 10-18

17. Background: Bias • Reverse Bias and Forward Bias • N connected with -ve, P with +ve : Forward Bias • Opposite polarity : Reverse Bias • increase in depletion region I-V curve I Reverse Forward

18. - - - - - - - - + + + + + + + + MOS CAPACITOR - + + N N N - - - - Oxide + + + + P P P + - - Accumulation Depletion Inversion Mobile electrons at the oxide interface. Immobile -ve ions in the solid Oxide + depletion two capacitors in series Simple Capacitor • Similar results if the ‘top’ N is replaced by metal • Originally metal was used • Metal-Oxide-Semiconductor structure or MOS structure

19. MOS FET • Transistor using Electric Field to control • Field Effect Transistor or FET • Made with MOS ==> MOSFET • Other types: JFET (Junction FET), MESFET etc N-MOSFET (NMOS in short) Gate (Base) Drain (Collector) Source (Emitter) + - N+ P N+ N+

20. MOS FET: Structure • NMOS: By definition, Source is at lower voltage than drain • PMOS: By definition, Source is at higher voltage than drain • NMOS: IDS (Drain to Source current) is positive • PMOS: IDS is negative NMOS Gate (Base) Drain (Collector) Source (Emitter) + - N+ P N+ N+

21. NMOS: Operation • Negative gate voltage: • Accumulation of holes in P region, near oxide • No formation of Channel NMOS Gate (Base) Drain (Collector) Source (Emitter) + - N+ - - - - + + + + P N+ N+

22. NMOS: Operation • Positive gate voltage: • Depletion of holes near the oxide • No channel formation NMOS Gate (Base) Drain (Collector) Source (Emitter) + - N+ + - P N+ N+

23. NMOS: Operation • MORE positive gate voltage • Inversion: Accumulation of electrons in P region (minority carrier is more than the majority carrier) near oxide • Formation of Channel NMOS Gate (Base) Drain (Collector) Source (Emitter) + - N+ + + + + - - - - P N+ N+ • Trapped charges in gate ==> Flash memory

24. NMOS: Operation • Threshold Voltage VT, Gate Voltage VG , Source Voltage VS and Drain Voltage VD. • If Source is grounded, then VDS is same as VD NMOS inversion Gate (Base) Drain (Collector) Source (Emitter) + - N+ + + + + - - - - P N+ N+

25. NFET Behavior • For VG > VT , Channel forms • (VG - VT )is the overdrive • Small shifts in VG causes large changes in IDS • VT depends on Doping in P and oxide thickness • IDS depends on VG and VDS • Analogy: Water flow (from MIT EE web site) • Source and Drains are two tanks, Channel is pipe connecting two tanks and Gate is the valve • VDS is the height difference between source and drain tanks • VG indicates the position of valve • Opening the valve more increases flow (electron concentration) • Increasing the height difference increases the flow (field)

26. NFET Behavior • Beyond a limit, increase in height VDS changes the behavior • No more increase in current flow (for a given VG)

27. VG-VT=0.6 V LINEAR SATURATION Saturation current VG-VT=0.4 V IDS VG -VT = 0.2V VT VG =VT VG CUT OFF NFET I-V curve When VDS is very large (> VG-VT) IDS VDS IDSAT depends on VG and on the gate length (channel length)

28. NMOS: Operation NMOS Gate (Base) Drain (Collector) Source (Emitter) + - N+ + + + + - - - - P N+ N+ • NOTE: Inversion layer will be thicker near source and thinner near drain

29. NMOS: Pinch Off NMOS Gate (Base) Drain (Collector) Source (Emitter) + - N+ + + + + - - - - P N+ N+ • When VDS is very high (= VG-VT), Inversion layer thickness becomes zero near drain • Pinch off • However, no barrier to current flow

30. NMOS: Beyond Pinch Off NMOS Gate (Base) Drain (Collector) Source (Emitter) + - N+ + + + + - - - - P N+ N+ • Beyond pinch off, increasing VDS does not cause increase in ID • However, channel length becomes shorter and there is slight increase in ID

31. MOSFET: Some issues • Above conclusions based on VS=0 (grounded) • Otherwise, VG refers to VGS • When the field is high, electrons have high energy • can damage the silicon/ oxide (gate) interface near drain • Hot Carrier Effect Gate (Base) Drain (Collector) Source (Emitter) + - N+ + + + + - - - - P N+ N+ • Reduce the doping concentration near Drain • Lightly Doped Drain (LDD)

32. MOSFET: Some issues • When channel is very short (gate length is short), depletion regions in source and drain may merge • short channel effect • increase doping to keep VT non zero • Refer to Device books for details of the above and other issues

33. MOSFET: Speed • The time it takes to switch a transistor ON / OFF decides the speed of a digital circuit • shorter Gate length ==> Faster switching ON/OFF Gate (Base) Drain (Collector) Source (Emitter) + - N+ + + + + - - - - P N+ N+

34. MOSFET: Device • If the base is also lightly doped N, it is depletion mode device (ON by default). Current schematic is Enhancement mode device (OFF by default). Most devices are Enhancement mode devices • Depletion devices in imperfect crystals (historical) Gate (Base) Drain (Collector) Source (Emitter) + - N+ + + + + - - - - P N+ N+

35. FEOL: MOSFET • Combination of PMOS and NMOS is called “Complementary MOS” or CMOS • When a voltage is applied to the gates, one transistor is on and the other is off

36. CMOS - Advantages • Scalable • Power consumption is low • Any any point of time, one of the devices is “off”