A Non-Coherent Multi-Band IR-UWB HDR Transceiver based on Energy Detection

1. A Non-Coherent Multi-Band IR-UWB HDR Transceiver based on Energy Detection Mohamad Mroué,Sylvain Haese, Ghaïs El-Zein, StéphaneMallegol and StéphanePaquelet 17th IEEE International Conference on Electronics, Circuits and SystemsDecember 15th, 2010Athens, Greece

2. Presentation progress • MB IR-UWB Transceiver for HDR Applications (Modulation Principles and Architecture) • Analog CMOS Pulse Energy Detector (Architecture and Performance) • Conclusion and Prospects

3. Presentation progress • MB IR-UWB Transceiver for HDR Applications (Modulation Principles and Architecture) • Analog CMOS Pulse Energy Detector (Architecture and Performance) • Conclusion and Prospects

4. Principles of the proposed system High data rate transmission with impulse radio ? • Impulse radio based solution duplicated on multiple sub-bands • Asynchronous treatment at reception based on energy detection • Amplitude modulation: On-Off Keying (OOK) • Non-coherent demodulation: energetic threshold comparison • To avoid inter-symbol interference: the pulse repetition period Tr must be greater than the channel delay spread Td • Extension to multiple bands: to increase the system capacity Band-pass filter Pulse detector ADC … 1 1 0 1 … Channel 1 0 1 1 Tr Pulse generator OOK modulation … 1 1 0 1 … Td (S. Paquelet et al., in joint UWBST IWUWBS, 2004)

5. 1 3.1GHz 10.6GHz 3.1GHz 10.6GHz 1 0 0 1 0 3.1GHz 10.6GHz 3.1GHz 10.6GHz 10.6GHz 3.1GHz 1 3.1GHz 10.6GHz 1 0 0 1 0 UWB HDR transceiver architecture • Transmitter architecture: filter bank implementation Measured transmission responses versus frequency for a 3.1-5.2 GHz octoplexer. • Advantages of the proposed architecture: • Relaxed hardware constraints: • Only coarse synchronization is needed • Energy based processing • Flexibility of the multi-band architecture: • Scalable data rate / power control • Radio resource management • Receiver architecture: pulse detector on each sub-band • (De)multiplexer involved in the MB-OOK UWB transceiver • No power division effect •  In-band insertion loss < 4 dB • No external bias (Only passive devices) • Identical (de)multiplexer for Tx and Rx

6. UWB HDR transceiver architecture • Transceiver’s components • Commercial monocycle pulse generator • Peak-to-peak amplitude into 50 Ωload: 3.29 V • Duration: 184 ps, center frequency: 5 GHz • Quadriplexer (3.1-4.2 GHz) • (De)multiplexer only based on filters • Identical (de)multiplexer for Tx and Rx • No external bias (Only passive devices) • No power division effect  No need of signal amplification (In-band insertion loss < 3 dB) • Mechanical etching process using low-cost organic substrate (RO3010) • Amplification stages • Total amplification level of 42 dB • UWB antennas • Conical monopole (Omni-directional) • Horn antenna (Directional with half power beamwidth > 50° in the 3.1-4.2 GHz)

7. Measurement results in LOS and NLOS configurations Omni-directional Antennas Directional Antennas

8. Presentation progress • MB IR-UWB Transceiver for HDR Applications (Modulation Principles and Architecture) • Analog CMOS Pulse Energy Detector(Architecture and Performance) • Conclusion and Prospects

9. Implementation study of the detector • Specifications: • Operation with large bandwidth (3.1-10.6 GHz) • Input detector bandwidth ~ 500 MHz • Low mass fabrication cost • Low power consumption and low complexity • The circuit must provide the pulse detection on each sub-band CMOS technology

10. Adopted squarer circuit • Squarer based on two MOSFETs • When biased with zero drain to source voltage in the triode region • The circuit is driven by balanced signals • Output current: • Condition : • M1 and M2 must perfectly be matched (K, a1, a2) • Avantages : • Simple design • No additional power consumption • Principle can be applied on all CMOS IC technologies

11. Integrator • Integrator • Current to voltage conversion and integration  directly around a capacitor • Current amplifier: • Low input impedance: square law operation of the first stage • High output impedance: integration and S/H stage

12. Integrator • Current amplifier • Input bandwidth ~ 500 MHz • Useful part of the squared signal pass to the integrator unaffected • Architecture based on current mirrors • Easy to implement • Reduced complexity • Low voltage and low power consumption • Integrator • Output capacitor • Current to voltage conversion • Signal integration Iamp Iin

13. Sample and hold circuit • Adopted architecture: open loop S/H circuit • Charge injection effects Sampling errors • Charge injection compensation: • CMOS switch • Minimum-geometry switches • Large capacitor • Switch architecture • Reset switch: low ON resistance rON • Short discharge time for the hold capacitor • Other switches: minimum (W,L) • reduce the charge injection effects • Output stage • Unity gain output buffer • High input impedance

14. Circuit performance • Noise performance • Noise level at the output of the detector • Included detector parts: squarer, current amplifier, switch (ON state) and the hold capacitor • Estimated noise level: ~ 1 % of the useful signal level • Imperfection effects study • Effect of the input impedance of the current amplifier on the squarer • Gain variation of the squarer as a function of the input impedance • Effects of the MOS transistors’ parameters variations • Squarer operation: • Effect on the gain of this stage • The square law function of the squarer is not affected • Current amplifier operation: Current offset and gain • A modification of the architecture permit to reduce the generated offset current

15. Pulse detector architecture • Time domain simulation • Simulator: CADENCE Spectre • Technology : AMS 0.35 μmBiCMOS

16. Pulse detector architecture • Pulse Energy Detector with two parallel stages for the integrator and S/H stages. • Time domain simulation • Simulator: CADENCE Spectre • Technology : AMS 0.35 μmBiCMOS • Tr = 15 ns, Ti = 13 ns, TReset = 3 ns , Ts = 8 ns Input pulse Integration Sampling Reset 1 0 1 1 0 1 Transmitted code:

17. Presentation progress • MB IR-UWB Transceiver for HDR Applications (Modulation Principles and Architecture) • Analog CMOS Pulse Energy Detector (Architecture and Performance) • Conclusion and Prospects

18. Conclusion and prospects • Conclusion • Functional tests of the communicating system in real environment • Comparison between the use of directional and Omni-directional antennas in LOS and NLOS configurations • Implementation evaluation of the proposed Multi-band IR-UWB system • MB IR-UWB receiver architecture LTCC technology (Low Temperature Co-fired Ceramic) CMOS Technology SiP approach (System in Package) Analog Front-End: LNA and VGA with an appropriate technology Power consumption: ~100 mW Filter bank: no additional power consumption Base-band: pulse energy detection Power consumption: ~ 40 mW

19. Thank you for your attention !

20. ITE-UWB HDRPrinciplesPerformances:optimal demodulation rule • Energy demodulation problem for OOK (one sub-band) • two symmetric hypothesis • Objective : minimise error probability knowing • and after estimating • Probability densities • où • Special demodulation threshold Optimal threshold • with S. Paquelet, L-M. Aubert et al, UWBST 2004, « An Impulse Radio Non-coherent Transceiver for High Data Rates »

21. Pe E/N (dB) ITE-UWB HDRPrinciples Performances/Comparisons • Coherent - RAKE receiver: • Energy recovered on few paths • whereas • Quadratic integration: • Whole available energy recovered • rake achieves comparable if it collects 33% to 40% of the whole available energy. • Extended Notion of OFDM • orthogonal carrier orthogonal pulses • intrinsic fading resistance • CM: IEEE Channel Models • 2: NLOS 0-4 meters • 3: NLOS 4-10 meters • 4: Extreme NLOS multipaths * without FEC S. Paquelet, L-M. Aubert et al, UWBST 2004, « An Impulse Radio Non-coherent Transceiver for High Data Rates »

22. Mean performance for a given received energy when considering the FCC limitations

23. Quadriplexer (3.1-4.2 GHz) • Mechanical etching process • Low cost organic substrate RO3010 • « Ceramic-filled PTFE composite » • Dielectric constant : 10.2 • Metallization thickness : 17 µm • Architecture • 1 Low pass filter • 4 bandpass filters • Based on resonators • No power division effect Intercept-point magnitude betweenadjacent sub-bands > 14 dB (S. Mallégol et al., EuRAD&EuMC, 2006)

24. In Size: 71 mm  62 mm Octoplexer (3.1-5.1 GHz) • ANR BILBAO Project (S. Mallégol et al., EuRAD&EuMC, 2006)

25. The first 4 pulses at the outputs of the 3.1 – 5.2 GHz octoplexer (Tx) Spread of the output pulses < 6 ns (< Td) Measurements and simulation results Measurements results Out1 3.1-5.2 GHz Octoplexer 3.1-5.2 GHz Octoplexer 3.1-5.2 GHz Octoplexer Monocycle-pulse generator LNA Non-filtered monocycle pulse Out8 Into 50 : Vpeak-to-peak = 3.29 V Duration = 184 ps CADENCE simulation results

26. Modified current amplifier architecture • Objective: to reduce current offset level generated at the output • Modifying the architecture of the current amplifier • Altering the positions of two p-channel and n-channel MOS transistors  Compensation of effects of MOS transistors’ parameters variations  The current offset is reduced by 4 to 5 times

27. Variation effects of MOS transistors’ parameters • Evaluation of the current offset variation generated at the output of the current amplifier • Variation of the threshold voltage VT and the transconductance factor K • Comparison between analytical and simulation results

28. Modified current amplifier architecture • New Monte-Carlo simulation results using CADENCE with variations on mismatch and both mismatch and process parameters mismatch mismatch & process