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Chapter 8 . Sequential machine

Chapter 8 . Sequential machine. x 1. 0. 1. 0. ••• •••. Z. 0. 0. 1. Serial Adder. ••• •••. x 2. 1. 1. 1. ••• •••. Output Z. Input X. Combinational circuit. M. Current state S. Next state S. M. Sequential machine M = ( I, O, S, , )

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Chapter 8 . Sequential machine

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  1. Chapter 8. Sequential machine

  2. x1 0 1 0 ••• ••• Z 0 0 1 Serial Adder ••• ••• x2 1 1 1 ••• ••• Output Z Input X Combinational circuit M Current state S Next state S M Sequential machine M = ( I, O, S, , ) I : set of input O : set of output S : set of states  (state transition) : I  S  S for i  I, s  S (i,s)  S’  : Output function, if  : I  S  O “Mealy machine”  : S  O “Moore machine”

  3. Mealy machine Moore machine I S I1 I2 ••• ••• In Output S1 S2 Sn Si Oj Moore machine  Mealy machine Mealy machine  Moore machine I S 0 1 I S 0 1 I S I S 0 1 0 1 Z Z I S I1 I2 ••• In 0 1 01 1 1 2 3 4 1 2 4 3 4 3 2 1 1 2 3 4 1 2 3 4 1/0 2/1 4/0 3/1 4/0 3/1 2/1 1/0 1/0 2/1 4/1 3/0 4/1 1/0 2/1 3/1 0 1 1 0 1 2 3 4 3’   1 2 4 3 4 1 2 3’ 4 1 S1 S2 Sn Next state/output Si/Oj • State equivalence and machine minimization. • Two finite state machine m1 and m2 are equivalent iff for any state of m1, say S1, there is some state of m2, say S2, such that starting with m1 in state s1 and m2 in state S2 and applying say sequence of inputs, results in an identical sequence of outputs from m1 and m2. In such case, S1 and S2 are called equivalent states.

  4. Simplification of completely specified machines The sets of equivalent states of a machine from a portion of the states of the machine. The minimal machine corresponding to this machine will have a state for each equivalence class of the original machine. The states, S1 and S2, are k-equivalent if for any input sequence of length  k, the same output seq. is produced regardless of whether S1 and S2 were the initial state. Two states which are not k-equivalent, are called k-distinguishable. P1: partition imposed by grouping states whose outputs agree for any input sequence length by 1. Compute Pi for i>1 such that two states Si and Sk are in the same block of Pi (i.e., are i-equivalent) iff Si and Sk are (i-1)-equivalent (i.e., in the common block of Pi-1) and for each input, the next states of Si & Sk are (i-1)-equivalent.(i.e., are in the common block of Pi-1) I S 0 1 Pk : partition imposed by grouping states whose outputs agree for any input sequence length of k. ABCDE A/0 B/0 A/0 C/0 A/0 D/0 A/0 E/1 A/0 E/1 (Produce the same output) We can say, D & E are equivalent state. (transform)

  5. I S 0 1 We can reduced state table.     /0 /0 /0 /0 /0 /0 /0 /1  reduced machine. We can say, minimal machine. (Same outputs) I S 0 1 (Same outputs & same state) ABCDE F E/0 D/1 F/0 D/0 E/0 B/1 F/0 B/0 C/0 F/1 B/0 C/0 Simplification of incompletely specified machines Two states, Si and Sj, a machine M are compatible iff for every input sequence applicable to both Si and Sj, the same output sequence will be produced whenever both outputs are specified, regardless or whether Si and Sj is the initial state. (outputs are not conflicting) While the equivalence partition consists of disjoint blocks, the subsets of compatible may be overlapping.

  6. 1- compatible  (different output) (1,3), (2,4) S I1 I2 I3 2- compatible 1 2 3 4 5 6 3/0 – 2/– – 4/0 6/– 5/1 – –/0 – 1/1 – 1/– – 6/– 4/– 5/– 6/– (1,5) 3- compatible (3,5), (4,6) 4- compatible (1,3) (already incompatible) Example) Compatible pairs of states (1,2) (1,3) (1,4) (1,5) (1,6) (2,3) (2,4) (2,5) (2,6) (3,4) (3,5) (3,6) (4,5) (4,6) (5,6) Maximal Compatible Set (1,2,6) (1,4) (2,3,6) (2,5,6) (3,4) (4,5) Set of maximal compatible : set of compatible states (i.e., a compatibility class) which cannot be contained in any larger compatibility class.

  7. We can find (from maximal compatible set) Lower bound required by the reduced machine  3 (to cover all states) (eg – {1,2,6},{3,4},{4,5}: the min # of maximum compatibles which cover all states) Upper bound : min (# of maximum compatible, # of original state)  6 (previous example) Suppose & pick (1,2,6) (2,3,6) (4,5) Require another state  we can’t find 3 state machine.  try another possible case or try find 4 state machine. a a a a b b b b c c c c a b c (2,3,6) (4,5) (1,2,6) (4,5) (1,4) Suppose & pick (1,2,6)   (3,4)   (4,5)   (4,5) (1,2,6) (1,2,6) (1,2,6) (1,2,6) (3,4) (4,5) (1,2,6)

  8. Reduced machine (only 3 state = lower bound)  minimum state machine 1- compatible a b c (A,C), (C,D), (B,F), (C,E)   /0 /0 /– /1 /1 –/0 /– /1 /– 2- compatible (A,D), (E,F) <closed cover> 3- compatible Cover : every state of the original machine must be included Closed : For any compatibility class and any input, the next state of all states in this class, must also be in a common compatibility class used as a state of the reduced machine. (B,C), (E,F) 4- compatible S I1 I2 I3 I4 ABCDE F C/0 F/– –/1 A/0 – – A/–B/0 – – E/– B/1 –A/– D/0 – B/1 F/– – – – E/1 A/1 D/1 Compatible pairs (A,B) (A,E) (A,F) (B,D) (B,E) (C,F) (D,E) (D,F) (A,B,E), (A,F), (B,D,E), (C,F), (D,F) maximum compatibility class

  9. Number of states in minimal machine lower bound : 3 upper bound : 5 We have to pick (C,F) (C,F)  (D,F)  (A,B,E) If we pick (C,F) then (D,F) will be another, then to make a 3-state machine. We have to choose(A,B,E) (C,F) (D,F) I1 I1 I1 I4 I4 I4 I3 I3 I3 I2 I2 I2 – (A,B,E) (D,F) (D,F) (A,B,E) (A,B,E) (C,F)or(D,F) (D,E) We can’t find a 3-states machine starting with (C,F) (C,F) (A,B,E) (A,B,E) (A,B,E) Next, only let C is a state. Start with C then (A,B,E), (D,F) – we can’t find a 3-state machine (A,F), (B,D,E) (B,D,E) I1 I3 I2 (A,F) (B,D,E) (A,B) • Add one more state If pick (C,F), (D,F), (A,B,E), (D,E) We can’t find a 3-states machine    

  10. Reduced table (D,E) S I1 I2 I3 I4  –/1 /0 /0 /0 /1/1/0 /– /0 /– /1 /1 /1 /1 /1 /1 (A,B,E) (D,E) (A,B,E) (A,B,E) or (A,B,E) Synchronous sequential machine – common clock Asynchronous sequential machine – non common clock What constitute input change I1 I4 Clock skew : different time between each circuit I3 I2 Flip-flop R/S R R   clock output transition Required input S R output transition ’ 0  0 0  1 1  0 1  1 0   1 ’ S 0   1 0 – 1 0 0 1 – 0 S

  11. J/K flip-flop D flip-flop T flip-flop output transition output transition output transition Required input J K Required input D Required input T 0   1 0   1 0   1 0 – 1 – – 1 – 0 0 1 0 1 0 1 1 0 even blocks of zero or odd blocks of one Sequential machine 0/0 1/0 1/1 0/0 0/0 0/0 1/0 B: in a sum of zeros, seen an odd # of zeros C: in a sum of ones seen an odd # of ones D: in a sum of zeros seem am even # of zeros E: in a sum of zeros seen an even # of ones A E B C D 1/0 0/1 1/0 Synthesis of synchronous sequential circuits 1. From the specification of problem, from a state table (or a state diagram) 2. Minimize the machine 3. Select a state assignment and determine the type of memory elements 4. Drive output transition and output tables 5. Draw a circuit diagram

  12. I S I S 0 1 0 1 Reduced          /0 /0 /0 /1 /0 /0 /0 /1 /0 /0 /0 /1 /0 /0 /1 /0 Example) y1y2 0 1 00 01 10 11 01/0 10/0 00/0 10/1 01/0 11/0 01/0 11/1 Let, =00, =01, =10, and =11, then  Y1Y2 I S 0 1 Y1 J1 K1 J1 Y2 J2 K2 ABCDE B/0 C/0 D/0 C/1 B/0 E/0 B/0 C/0 B/0 C/1 x y1y2 0 1 0 1 0 1 x y1y2 0 1 x y1y2 0 1 0 1 0 1 J1=x, K1=x’, J2=x’+y1, K2=x+y1’ 00 0  0 1 – – 00 0 1 00  0 1 0 – – 01 0  0 1 – – 01 0 1 01   – – 1 1 10  1 – – 1 0 10 – – 10   1 1 – – 11  1 – – 1 0 11 – – 11 1 1 – – 0 0

  13. Output (Z) x y1y2 0 1 x Z Combinational Circuit Combinational Circuit Q 00 0 0 y 01 0 1 Z=y1y2x’+y1’y1x 10 1 0 M 11 0 0 Iterative networks: a cascade of identical circuits (or cells) x y1 Z xk•••x2x1 Zk•••Z2Z1 y2 M yi Yi x1 x2 xk Q Q Q Q y2 y1 J1 J2 ••• ••• K2 K1 Z1 Z2 Zk

  14. Asynchronous Sequential circuit Z I Total state: next state equal to the present state. Combinational circuit Stable state Yi yi State table One stable state P.S. Ij   Si Primitive flow table assumption: Only one stable state per row, and outputs are specified only for stable state. Prob. 11-9 l bar

  15. x1x2 state 00 01 10 11 A A/0 B No bar under beams or between beams B C B/0 D One bar is under B1 C C/0 E Short bar between beams D F D/0 Long bar under both beams E G E/0 H Short bar under B2 only F A F/0 I Long bar under B2 only and nothing under B1 G G/1 J Short bar passed both beams & nothing under B1 H J H/0 Short bar under B2 and another bar under B1 I I/0 Long bar under B2 and another bar under B1 J C J/1 D Short bar just cleared B2 and another under B1 x1x2 00 01 10 11  /0 /1   /0/1  /0  /1 /0 /0 Maximal compatible class (ABCI), (ABDFI), (CHJ), (DGI), (EG), (EH), (F,J) Best closed cover (ABCI), (DFI), (EG), (DHJ)

  16. State assignment in asynchronous sequential circuit Z I Combinational circuit Not common clock yk Y1 y1 Yk Race occurs anytime multiple state variables must change during a state transition Critical race : A race which may result in reaching an erroneous stable state (vs. Non critical race) The assignment of multiple vars must be such that the circuit will operate correctly even if different delays are associated with the secondary elements.   x1x2 y1y2 x1x2 y1y2 00 01 10 11 00 01 10 11 D C D D 10 11 10 10 ABCD B D C C 01 10 11 11 A A A D 00 01 11 10 00 00 00 10 C C C C 11 11 11 11 If x1x2=00 current state y1y2=00  y1y2=11(stable state) If x1x2=01 current state y1y2=11  y1y2=00 or 10

  17. x1x2 y1y2 00 01 10 11 11 10 11 11 01 11 10 10 00 00 00 11 A 00 B 01 C 10 D 11 10 10 10 10 For valid state assignment, each transition is accomplished by change of secondary state 1. In which only one secondary variable change 2. In which a multiple change of secondary variables does not result in a critical race Multiple transition time state assignment 00 01 10 11 00           01 10   00 01 10 11  11 000    000 001 010 011 100 101 110 111 000 000 010 – – 000 – – – – – – 010 001 010 – – 101 001 – – – – 000 000 000 – – 100 – – – – – – 001 001 110 – – 100 – – 100 – –        001 010 Same we can say (, ), (, ) adjacent         110 101  100 avoid race

  18. Single transition time state assignment 000 00 01 10 11 100 001 010 001     000 001 010 011 100 101 110 111 000 000 000 011 000 000 000 – – 011 011 011 011 101 101 101 101 000 000 000 000 000 000 110 – – 101 101 110 110 101 101 110 110   Y1 = f(y1, y2, y3, x1, x2) Y2 = f(y1, y2, y3, x1, x2) Y3 = f(y1, y2, y3, x1, x2) 010 100   101 011   010 111 100 111 110 13. State Identification and Fault-Detection Experiment a machine : reduced, completely specified a machine (block box) I Z A block box which cannot inspect the internal device and their interconnection.  The experiment consists of a set of inputs and their corresponding output sequences.  Identify the unknown initial state and the final state of the machine.  Equivalent to fault-detection problem to determine whether the machine is operating correctly.

  19. I S I S 0 1 0 1 ABCD ABCD A/1 B/0 B/0 C/0 C/0 D/0 D/1 D/1 C/0 B/0 D/1 C/0 A/1 A/0 C/0 D/0 (A, B, C, D) 1 0 0 0 1 (A, B, C, D) (A, D) (C) 1 0 (C) (A) (A, B, C, D) (A, B, C, D) (B, C, D) 1 1 1 0 0 0 (B, C, D) (C, D) (C, D) (D) • Homing sequence: to identify the final state. • The input sequence which, when applied starting in any initial state, allows the final state to be uniquely determined by observing the output sequence produced. Input seq: 00 Output seq: 01 A Output seq: 10 C All machine has homing sequence • Synchronizing sequence: the input sequence which drives a machine to a known state, independent of the output sequence produced. 111: synchronizing sequence

  20. (A, B, C, D) I S 0 1 ABCD A/0 B/0 B/1 D/0 C/1 A/0 C/0 A/1 (A, B, C) (A, B, D) (A, B, C) (A, B, D) (A, B, C) (A, B, D) This machine does not have synchronizing sequence 1 1 1 0 0 0

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