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Reconfigurable Architectures

Delve into the world of reconfigurable computing with a focus on FPGA architectures, advantages, properties, and evaluation conclusions. This comprehensive paper discusses cluster-based FPGA designs and their impact on speed, area tradeoffs, memory/logic interconnections, and more. Gain insights into routing architecture, memory resources, and compile time considerations. Discover the enhanced architecture supporting memory connections and programmable switches.

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Reconfigurable Architectures

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  1. Reconfigurable Architectures Sankalp Kallakuri Vaishali Damle

  2. Papers selected • A. Marquardt,"Speed and Area Tradeoffs in Cluster-Based FPGA Architectures", IEEE Transactions on VLSI, Feb. 2000.  • S. Wilton et. al,"The Memory Logic Interface in FPGA's with large Embedded Memory Arrays", Transactions on VLSI, March 1999.

  3. Papers Selected • H. Zhang,"A 1V Heterogeneous Reconfigurable Processor IC for Baseband Wireless Applications", IEEE Journal on Solid State Circuits, Vol. 35, Nov 2000, pgs 1697-1704. • B. Salefski,"Re-Configurable Computing inWireless",Design Automation Conference, 2001.

  4. Reconfigurable Architectures • What is reconfigurable computing? • Advantages of reconfigurable computing • Reconfigurable Hardware

  5. FPGA’s as hardware • Field Programmable Gate Arrays • Properties – • On the fly programmability • Partial programmability • Externally-Visible internal state

  6. Cluster-Based FPGA’s • Logic cluster – group of logic elements connected with high speed local interconnections. • Basic Logic Elements (BLE’s) • Local Routing for BLE’s

  7. Basic Architecture • Island-style FPGA’s • Pads = floor(2 * sqrt(Cluster size)) • Routing Architecture

  8. Area and Delay Results • Area – affected by intercluster routing area and cluster area • Delay – intracluster and intercluster connections • Compile time

  9. Large Embedded FPGA’s • To implement large circuits or entire systems • FPGA with on-chip memory support

  10. Baseline Architecture • Memory resources • Logic resources • Memory/logic interconnect block

  11. Memory/Logic interconnect • Flexibility • Affects the area • Affects the delay • Affects the track requirements

  12. Enhanced Architecture • Supports memory to memory connections • Programmable switches between neighbouring memory arrays • Evaluation

  13. Conclusion

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