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Status of the LPC Phase-II upgrade activities

Overview of ATLAS-LPC annual meeting at Domaine du Marand in November 2015, detailing progress, challenges, and next steps in the LHC luminosity upgrade project's second phase. The focus is on R&D studies, mechanical developments, PMT active dividers, remote HV system, and front-end enhancements.

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Status of the LPC Phase-II upgrade activities

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  1. Status of the LPC Phase-II upgrade activities ATLAS-LPC annual meeting Domaine du Marand, 2015 November 6th François Vazeille • Geneva, 29 October 2015: “LHC luminosity upgrade project moving to next phase“ • CERN press release • First phase completed (2011-2015): design study • by a large collaboration CERN + Russia, Japan and USA • Second phase started: development of industrial prototypes. • Ultimate goal: • HL-LHC  10 times more collisions in 2025 than the nominal LHC . The LPC upgrade activities are made in an official context (CERN, ATLAS, IN2P3) and should maintain the positive role played by our team since the very beginning, both in ATLAS (and before) and in the upgrade works (2004: studies, 2008: R&D).

  2. ● 4 R&D studies made by our team: Two are completed, two are in progress. ● No R&D failed … even though a failure is always acceptable in R&D projects.  We made good choices.  We worked rather well … despite a reduced technical manpower (I will come back to this point). ● Official follow-up: - At CERN: TileCal meetings (Vidyo meeting every Wednesday + Tilecal weeks) + Expert weeks (Hall 175) + Test Beam + official ATLAS papers. - At IN2P3: annual upgrade meeting. - At LPC: CSAT meetings every 6 months, (“Commission de Suivi des Actions Techniques“) + Scientific council (Every 2-4 years). - In the LPC team: meeting every Friday. • Mechanical studies: Mini-Drawers and Handling Tools • PMT Active Dividers • Remote High Voltage System • Very Front End and Front End Readout Completed In progress

  3. Mini-Drawers and Handling Tools ● Concept and validation of Mini-Drawers ● Concept and validation of Handling tools: Slider and Basket Contacts on 4 rings

  4. Concepts transferred to Barcelona and now Bucharest: pictures from the Test Beam Mini-Drawer partially equipped with FATALIC Slider and Basket in position (David Calvet pictures)

  5. PMT Active Dividers ● HL-LHC constraints: Higher minimum bias levels  higher current flow in PMTs  non-linear working of PMTs with current PMT Dividers. ● Goal: to recover a very good linearity for the highest currents in PMTs, in particular for high energy jets (more numerous in HL-LHC). ● Solution: to replace the current passive Dividers by active Dividers Current Dividers: only passive components  No radiation sensitivity. Active Dividers: Transistors and Diodes in the last 3 stages  Radiation sensitivity.

  6. ● Main results ▪ Comparison of non linearities versus current - At HL-LHC: max currents  10 µA (If Luminosity = 5 times nominal LHC) - Negligible NL with active Dividers at least up to 150 µA. Set of 10 dividers ▪ Divider Test Bench now compatible with passive/active Dividers Test Bench ▪ Active Dividers fitting radiation tests (NIEL: CEA Dijon, TID: Brookhaven). ▪ 350 active Dividers presently in ATLAS (MBTS + Crack scintillators). ▪ 2 Internal ATLAS Notes Concept of active Dividers and tests: ATL-TILECAL-INT-2014-005 Radiation certification: ATL-TILECAL-INT-2015-001

  7. Remote High Voltage System ● Current performance in RUN 1 (Loic Valery’s thesis + Internal Note) - HV Stability of  100 mV (Mean applied PMT HV  690 V). - Problematic channels  0.6 %. - No precise knowledge of HV noise and HV induced noise on readout noise. ● Goal: To reproduce the current performance with a 100% reliability on the HV supply of the 9852 TileCal PMTs, with increased radiation level. ● Solution: to locate all the electronics in the USA15 counting room, by using the same electronics + long multi-conductor cables for supplying PMTs  HV Remote system. Remote option Current (embedded) option

  8. ● Prototype set-up 100 m long cable HV Bus cards Current loop Phase-II loop With 2 challenges: - HV induced noise due to both long cables and Transistors both in the HV loop scheme and in active Dividers  HV regulation loop without Transistors for Phase-II. - HV regulation stability.

  9. ● Results from tests at LPC and at CERN (Radiation aspects out of order) HV noise  2.5 mV at 700 V HV/HV  2.6-2.7 10-6 in the HV range [550, 850 V] HV induced noise on readout within readout data uncertainties HV stability  90 mV + Waiting for next results from the last Test Beam. ● Next steps: - Test beam analysis. - Choice and routing of final HV multi-conductor cables. - Final prototype study with Lisbon. - Final decision between the 2 options: Remote HV (LPC) and Embedded (ANL). ● Internal ATLAS Note ATL-INT-TILECAL-2014-082 + Poster and proceeding at TWEPP workshop at Lisbon (September 28-October 2).

  10. Will be published in JINST (8 pages) … after comments of reviewers.

  11. Very Front End and Front End Readout ● Goals: ▪ To reproduce current performance (and even better: noise, linearity, dynamics). with increased pile-up and radiation. ▪ To take benefit from Phase 0 experience and from technologic progresses. - Reducing the number of cards, connectors, cables. - Using ASIC chips, GBT fibers. - Remote trigger in USA 15 room: data towards the USA15 room at LHC frequency. - To keep a reasonable cost. ● 3 Concurrent options with common components ▪ Option 1: discrete component, by Chicago (Evolution of the current readout). ▪ Option 2: Special design of a new ASIC, by LPC. ▪ Option 3: Evolution of a CMS chip, by Argonne. Very Front End Main Board Daughter Board sROD + Trigger Chicago LPC, ANL Stockholm Chicago, LPC Valencia Front End electronics Back End electronics

  12. ● Solution: Custom ASIC IBM 130 nm technology ▪ Separate studies of analog part (Current conveyor + 3 shapers H, M, L gains) and digital part (ADC). ▪ Then whole design: FATALIC 4.

  13. ▪ Main Board studied by LPC for the options 2 (LPC) and 3 (ANL): 16-layer card. ● Results from tests at LPC and at CERN Test Beam (To come). ▪ Static tests made by µ-electronics staff at LPC. ▪ Dynamic tests on a special Test Bench at LPC by electronician and physicists. Optimal filtering study 

  14. ▪ Test beam analysis - Study of PMT and FATALIC pulses - Study of digital data from FATALIC: in progress. ▪ Talk of Laurent Royer at TWEPP 2015, but no proceeding written. ● Next steps - To complete the Test Beam analysis. - To restart tests at LPC (Diode and CIS). - To complete the association Main Board/Daughter Board + Tests at LPC. - To build the Optimal filtering  True performance with/without Minimum Bias and pile-up. - Radiation tests. - Test Beam in 2016.

  15. Conclusion and next steps ● 4 R&D projected launched by LPC. ● 2 R&D completed: ▪ Mini-Drawers and handling tools: agreed by collaboration, now transferred to Bucharest, while keeping an eye on the tools. ▪ Active Dividers: agreed by collaboration for the Phase II, with 350 Dividers already in ATLAS for Run 2. ● 2 R&D in progress: ▪ Remote HV system: performance fitting specifications, choice to make with the ANL embedded option (Former LPC design). ▪ FATALIC project: performances always under tests, choice to make with the 2 other options (Chicago and Argonne).

  16. ● Two crucial years coming Choice !

  17. ● Manpower and funds for 2016-2017 ▪ Manpower: - Physicists (Full time or partially: 1.2 ?): Louis Franck Romain Madar Dominique Pallin François Vazeille - Engineers and technicians (2.5) - Electronics: Romeo Bonnefoy (Full time) + Technicians. - µ-electronics: µ-electronic staff (chaired by Laurent Royer) in stand-by waiting for an extension … that will need to start a new action. - Mechanics: François Daudon (Very partially) + Technicians almost in stand-by, even though contacts are foreseen with Bucharest. Question: where are the priorities in our laboratory ? ▪ Funds

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