Status of work for Phase 1 DT upgrade

1. Status of work for Phase 1 DT upgrade Muon Barrel Workshop C. Fernández Bedoya on behalf of DT Upgrade group May 6th, 2011

2. C. Fernández Bedoya May 6th, 2011 2 DT Upgrade plans PHASE 1 (2013-2014) * Replacement of theta TRB (Trigger boards) * Relocation of Sector Collector from the cavern (UXC) to the counting room (USC) PHASE 1 following steps (not strictly tighten to LHC shutdowns): * Replacement of DTTF (DT Track Finder) * Redesign of the TSC boards (Sector Collector trigger) * Replacement of the ROS boards (Sector Collector read-out) PHASE 2 * Connection with the tracker in the Level-1 trigger system * Replacement of Minicrate electronics (aging…)

3. C. Fernández Bedoya May 6th, 2011 3 LHC schedule 2010-2022

4. C. Fernández Bedoya May 6th, 2011 4 LHC schedule 2010-2022 Present rumors… We should not plan accordingly though!

5. C. Fernández Bedoya May 6th, 2011 5 DT Phase 1: Replacement of theta TRB F. Montecassiano MOTIVATION * Large number of TRB failures during installation and commissioning of the detector (1%) * Failure rates related to thermal stress of the BTI ASIC bonds (repeated power cycles) * Although a large number of BTI spares were produced, mortality was high and we remain with 3% spares * We need to enlarge the number of BTIM spares: * BTIM technology is obsolete, no more ASICs can be produced * Migration of the BTIM algorithm to an FPGA * Under Padova´s responsibility (R&D since a few years).

6. C. Fernández Bedoya May 6th, 2011 6 DT Phase 1: Replacement of theta TRB F. Montecassiano PRESENT STATUS * They have successfully integrated one full BTIM in one FPGA (4 full BTI inside an Actel ProAsic3 A3PE300) => 8 FPGAs per TRB * Radiation tests have been performed in most of the devices and no major problem was found: - FPGAs Actel A3PE3000 (8 per board) - IC MAX4375 current-sense supervisor (1 per board) - IC DS18S20 1-wire digital thermometer (1 per board) - Power MOSFET PMOS IRF7425 (1 per board) * Pending: -IC DS2450S 1-wire A/D + remote controlled switches (2 per board) -IC LTC3251 charge-pump step-down low noise (8 per board) to be tested with neutrons this summer * Unfortunately it seems that Microsemi/Actel 65nm could be not in time for this project (it would have reduced from 8 FPGAs to 1 FPGA per board) (Samples only available beg. 2012)

7. C. Fernández Bedoya May 6th, 2011 7 DT Phase 1: Replacement of theta TRB PLAN F. Montecassiano * Produce new theta TRB to substitute all the boards in MB1 station (50 chambers) => ~100 boards - Option 1 is changing all MB1 and it is driven by detector uniformity and upgrade considerations. - Option 2 is driven by maintenance and access considerations/concerns (various stations in YB+/-2). * Make sure we have a good testing system ready (during 2 years shutdown cooling, power and other central services would likely not be available) - Impact of improving the resolution has been studied (no big improvement at present but possibility is open)

8. C. Fernández Bedoya May 6th, 2011 8 DT Phase 1: Replacement of theta TRB F. Montecassiano SCHEDULE • 2011 Prototype test- 2012 Production + parts procurement- 2013-2014 Bench Test + REPLACEMENT Assume replacement takes ~1 chamber/day => 12 days with full access to each wheel (Assume max 3 months full replacement 1 station)

9. C. Fernández Bedoya April 14th, 2011 9 DT Phase 1: Relocation of SC crate • Motivation is not the physics performance but the fact that aging and other risks may jeopardize detector operation and contribute to an accelerated degradation • We believe is a necessary step to allow future upgrades • Make a “simple” 1 to 1 copper to OF conversion at UXC Low impact modifications: compatible with present system and with possible future upgrades Present system Proposed upgrade

10. C. Fernández Bedoya May 6th, 2011 10 DT Phase 1: Replacement of theta TRB PRESENT ARRANGEMENT - Responsibilities assigned according to previous know-how - Lack of manpower basically everywhere - In contact with other institutes that may be willing to participate CuOF in UXC: Torino with help from Padova for Slow Control Fibers layout and installation: Torino Integration in USC: Nobody at present OFCu in USC for RO: Madrid OFCu in USC for TSC: Bologna

11. C. Fernández Bedoya May 6th, 2011 11 DT Phase 1: CuOF G. Mazza, G. Dellacasa, S. Masselli

12. C. Fernández Bedoya May 6th, 2011 12 DT Phase 1: Replacement of theta TRB

13. C. Fernández Bedoya May 6th, 2011 13 DT Phase 1: CuOF Open Questions POWER CONSUMPTION AND COOLING • - Estimated power budget <1kW, similar to present system • - Possibility to reduce input voltage from 5.2V to 3.3 V to reduce power consumption • Improve mechanical design is possible to optimize cooling performance INPUT CABLES -RJ45 connectors have latch in opposite direction in ROS and TSC => To have identical CuOF we need to redo the layout of the LVDS cables (hard work) POWER DISTRIBUTION -Independent power to ROS and TSC CuOF to minimize the impact of a failure in 1 A3100? => How is the power going to be distributed inside the crate? => We want to modify the A3100 to have two independent outputs? SLOW CONTROL -In principle, few bandwidth required and slow protocols such as I2C acceptable. -Padova has offered help in the design of the Slow Control interface. Expecting to hear news. OUTPUT FIBERS -8 MTP connectors could be a problem for matching to USC depending on the OFCu option

14. C. Fernández Bedoya April 14th, 2011 14 DT Phase 1: CuOF Open Questions

15. C. Fernández Bedoya April 14th, 2011 15 DT Phase 1: CuOF Schedule

16. C. Fernández Bedoya May 6th, 2011 16 DT Phase 1: Fibers >500 kCHF? -No space for the patch pannels Options: -Blowing fibers from CERN -72 connector cable -144 connector cable 5000 €/cable (~300 k€) but large uncertainty in the fan-outs -Not yet an estimation -Fit the connectors in the cable chains? Schedule: -Fibers (and patch panels) should be purchased 6 months in advance -One fiber to test probably should be purchased before mid 2012 -Installation time ? -End 2013 Commissioning

17. C. Fernández Bedoya April 18th, 2011 17 OFCu proposals Possibilities: 1. Use the empty slot (where the ROS or TSC previously were allocated) for the OFCu => it means purchasing 20 crates instead of 10 => besides money (around 12keuros/crate), it means doubling the required space in USC…. 2. Install an additional crates with the OFCu => 10 9U VME crates + N crates unknown size 3. Use the rear transition modules of the 9U VME crates

18. C. Fernández Bedoya April 18th, 2011 18 OFCu rear transition modules We remain with 10 crates in total (as before): READOUT 5 VME crates 9U 12 ROS/crate 1 crate /wheel 12*4 A + 3 A= 51 A ROS ROS ROS ROS ROS ROS TRIGGER 5 VME crates 9U 12 TSC/crate 1 crate /wheel 12*10 A + 3 A= 123 A TSC TSC TSC TSC TSC TSC Power supplies 5V@115 A, 5V@230 A, 5V@345 A (no problem for current needs) Cooling to be verified

19. C. Fernández Bedoya April 18th, 2011 19 OFCu rear transition modules 6023 Wiener ROS / TSC OFCu - Rear transition modules can be 6U or 9U - For the 9U modules we need to discuss with Wiener the location of the power supply and the extension of the fan tray (already in contact)

20. C. Fernández Bedoya April 18th, 2011 20 OFCu rear transition modules 6021 Wiener Splitting ROS and TSC implies modification of the TIMBUS backplane (J3) * Got no answer regarding use of TSC data, but I think it would be good to keep it if possible (for commissioning of the system after changes (remember DCC will also be modified)) * The rear transition module could include another link for the TSC-ROS exchange: - 1 extra fiber/OFCu - 60 fibers to be routed from TSC to ROS location

21. C. Fernández Bedoya April 18th, 2011 21 OFCu rear transition modules Ethernet cables: 8/board => 96/crate OFCu Input optical fibers From the back of the rack

22. C. Fernández Bedoya April 18th, 2011 22 READ OUT OFCu rear transition modules ROS OFCu Power and slow control from J2 or P0? (if signals are bussed through the backplane) 25 channels/board -Pluggable OF receivers -Reusable for new ROS/TSC -12 channels -aprox 28 euros/channel (340 € ) J3 FPGA? 12 ch TSC 16 bit parallel data Ros_ready/trg_strobe Clock40MHz 12 ch TSC Deserializer 25th ch TSC input Dual SFP receiver

23. C. Fernández Bedoya April 14th, 2011 23 DT Phase 1: OFCu schedule -The pluggable 12-MTP receivers can be reused for new TSC and new ROS -An additional transmitter can be used in some rear transition modules to fan out the input signals to operate simultaneously old and new TSC/ROS SCHEDULE Q4 2011 Prototype production Q1-Q2 2012 Prototype validation Q3 2012 Procurement parts Q4 2012 Final board production Q3 2013 Installation and commissioning

24. C. Fernández Bedoya April 14th, 2011 24 DT Phase 1: Summary -TRB replacement is going ok and schedule looks reasonable -SC relocation architecture is far from being finalized We wanted to have an executive plan by the end of May: we haven´t advance much We need to start taking coherent decisions if we want the schedule to fit

25. BACK-UP

26. LINCO DT Sector Collector - 2 SC crates per wheel - Located in tower racks in UXC level 2 Near - 60 ROS and 60 TSC boards in the system (1 per sector) - Complex electronic system - Main elements: LINCO, TIM, ROS, TSC

27. C. Fernández Bedoya April 14th, 2011 27 DT Upgrade plans DISCLAIMER • * All of our Phase 1 upgrades are focused on technical reasons • * LHC 2010 has proven that DT performs superbly • * It is a wonderful and unique detector: • Although based on drift tubes (drift time of 400 ns), it has proven from the very beginning to provide a robust, efficient, pure trigger with synchronization and timing information with uncertainty well below 1 ns. • Goal for Phase 2: • * Multiple scattering limits pt resolution in muon system • * Priority at higher luminosity: • -reduce low momentum muon feedthrough L1: Increasing threshold not very effective High Level Trigger (SW) Big improvement when Tracker is used

28. C. Fernández Bedoya April 14th, 2011 28 DT Phase 1: Fibers layout * Space available for routing the fibers is tight but existing * Passing of connectorized fiber imposes constrains on the fiber selection * Latency of trigger chain is also an important concern

29. C. Fernández Bedoya April 14th, 2011 29 OF input stage In principle, there is enough space below the false floor in S1 USC to recover extra cable lengths (though it depends on the exact racks to be used). Main problem is to allocate the SC crates in S1: -10 SC crates 11U each -To minimize L1A latency, they should be close to DTTF racks (S1D01 and S2D02) -In DT racks at present there is only space to allocate 6 SC crates (and not very close to DTTF)

30. C. Fernández Bedoya April 14th, 2011 30 DT Phase 1: Integration in USC Blowing technique patch panels Structured fibers patch panels • Long list of tasks: • - Arranging of the fibers and the patch panels • - Choice of the optimal form factor • Estimation of the trigger chain latency • - Allocation of the crates in USC • Estimation of the power dissipated and cooling capability

31. C. Fernández Bedoya April 18th, 2011 31 TRIGGER OFCu rear transition modules Why the trigger boards would be different?: * Routing to the RJ45 connectors is different (4 pairs/RJ45 instead of 3) * TSC Output data (serialize, transmit), could be implemented with different firmware in the FPGA * 32/40 inputs instead of 25: -Either you use a third 12-channel receiver (=> 9U board instead of 6U) -Or you use 17 boards/crate in a particular arrangement: Receiver Signal Detect: if you don´t have input in one of the channels SD=0… better to fill up all the receivers

32. C. Fernández Bedoya April 18th, 2011 32 OFCu Patch pannels Just to start getting ideas… Example of a “home made” patch panel in USC which apparently houses 1440 fibers in 4U