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A Monolithic Pixel Detector in High-Voltage Technology

A Monolithic Pixel Detector in High-Voltage Technology. Ivan Peri ć University of Mannheim. This work draws on the results from an ongoing research project commissioned by the Landesstiftung Baden-W ürttemberg. Overview. Introduction to the high-voltage CMOS process

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A Monolithic Pixel Detector in High-Voltage Technology

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  1. A Monolithic Pixel Detector in High-Voltage Technology Ivan Perić University of Mannheim This work draws on the results from an ongoing research project commissioned by the Landesstiftung Baden-Württemberg

  2. Overview • Introduction to the high-voltage CMOS process • The idea behind the HV monolithic pixel Pixel electronics • Electrical tests • Noise • Threshold dispersion • Time over threshold • Measurements with radioactive sources • Estimation of the average MIP signal • Images • Outlook VERTEX 2006

  3. n+ High-Voltage Technology Two commonly used devices G S D Low-doped N-well n+ n+ n- Channel Large depleted zone Asymmetrical high-voltage NMOS p- High voltages up to 50 – 70V P-well implanted inside the N-well G B S D n+ Channel p- n- Deep N-well Vertical HV NMOS p- VERTEX 2006

  4. Floating CMOS (Cross-Section) • Properties • of the chosen technology • Maximal nominal • reverse bias of • deep N-well/P-substrate • diode: • 50 V • Depleted area of the diode: • maximal ~ 9m • expected average MIP signal • in the depleted zone: • 703 e • Minimum gate size: • 0.35 m Shallow N-well P-well P-well Deep N-well 50 V 9 m P Substrate VERTEX 2006

  5. Monolithic Pixel Detector in HV Technology Negatively biased P-substrate 4 pixels Pixel-electronics inside the cathode (N-well) Sensor cathode (N-well) VERTEX 2006

  6. Test Chip • The first test-chip have been implemented in a 0.35 m HV CMOS Process • Motivations • - to investigate the properties of deep N-well/P-substrate diode asa particlesensor • to demonstrate that it is possible to implement complex CMOS pixel electronic in the diode cathode • (The electronics can involve • - signal amplification, • - continuous bias/reset, • - threshold discrimination, • - hit bit storage • - time stamp electronic) VERTEX 2006

  7. Pixel Electronic as implemented in the Test Chip 3.3 V CR-RC Comparator Latch Bus driver CSA Readout bus Tune DAC AC coupling -50 V HV N-well P-substrate • The challenge: N-well is the sensor cathode and the carrier for the PMOS transistors at the same time • - Biasing of the N-well • Signal cross-talk • Prevention of the latch-up VERTEX 2006

  8. Amplifier Capacitive feedback: 0.9 fF (drain diffusion) + 1.3 fF (metal-metal parasitic) N-well c Load bias a N-well 420 fF In Out d 10/0.6 d Cascode bias P-Substrate Bias 9A High gain CSA The cross-talk: every P-diffusion (a, b, c, d) is capacitively coupled to the sensor Non-standard design VERTEX 2006

  9. Feedback Current Output Volt. Continuous Reset Bias circuit Bias 30 pA Continuous feedback with limited current* In Out *  Discharge with constant current ToT VERTEX 2006

  10. Disable CR-RC Shaper From now on, only NMOST… 30 pA Base line bias 0.86 nA Base line Base line bias 22.1 fF (poly) Amplifier out 0.6 nA Base line 7.6 fF (par.) Foll. bias CR-RC Threshold bias Threshold Pulse length is the linear measure of the input signal amplitude Tune DAC Tune VERTEX 2006

  11. Simulation Response to the signal of 1660 e Simulated amplifier output without parasitic capacitances Simulated amplifier output with parasitic capacitances VERTEX 2006

  12. Comparator and Latch Differential current logic with NMOS diode as load to avoid digital cross-talk Comparator/Buffer Latch OutN OutP OutP OutN InN InP Bias SetN 6A SetP ResN ResP Bias VERTEX 2006

  13. Pixel Top-View Bias (PMOS) Amplifier and FB (PMOS) Injection Capacitor FB (NMOS) Input Capacitor Amplifier (NMOS) Feedback CR-RC Shaper P-Well Select Reset 4 RAM Cells (NMOS + PMOS) All-NMOS Comparator NMOS Latch and Bus Driver Bus DAC VERTEX 2006

  14. Detector Capacitance The large detector capacitance limits the performances of the detector C(N-well/P-sub) ~ 38 fF C(N-well/P-well) = 180 fF! VERTEX 2006

  15. Test-Chip Scheme Test pulse Disable Mux + shift register Bias DACs Reset Select Load DAC #2 Mux + shift register DAC bits Sensor Electronic ToT output Digital output VERTEX 2006

  16. Noise (Theory) CF ~ 2.2 fF RF ~ 0.79 G CZ ~ 22 fF RZ ~ 0.060 G CFOLL ~ 7.6 fF RFOLL ~ 0.056 G F RB CF RF Z FOLL Comparator CZ RFOLL Cinj CSA CFOLL RZ ~Sn(CDET)2 ~Sn(RF)2 Z F FOLL Z F FOLL   Input current noise (spectral power density) Input transistor noise (SPD) VERTEX 2006

  17. Noise (Measurements) Regular pixel: 85 e Diode: 30 e VERTEX 2006

  18. Threshold Dispersion Measured sigma of 75 e Dispersion of tuned thresholds remains unchanged VERTEX 2006

  19. Time over Threshold Output signal Threshold Time over threshold Fit-function: VERTEX 2006

  20. Fe-55 Diode Regular pixel Decrease of depleted zone reflects in the smaller peak VERTEX 2006

  21. Spectra of the Sr-90 and Co-60 Sr-90 Co-60 2.283 MeV (0.935 MeV) 0.546 MeV (0.196 MeV) 1.333 MeV 0.316 MeV 1.173 MeV L=450 m VERTEX 2006

  22. Filtering of low-energy Electrons (Sr-90) (0.935 MeV) 0.546 MeV Plastic 1.9 mm 2 mm (2-2.1 MeVcm2/g) =0.9 g/cm3 (~0.57 MeV) Si 0.7 mm (1.6-1.9 MeVcm2/g) (MIP: 1.5 MeVcm2/g) =2.3 g/cm3 (~0.28 MeV) VERTEX 2006

  23. a) b) Sr-90 a) b) MIP Signal: 2000e/1.17 = 1710 e Low energy peak: 1.080 e VERTEX 2006

  24. Bias Voltage and Co-60 High energy peak moves to lower energies when bias voltage decreases VERTEX 2006

  25. Bias Voltage and Co-60 High energy peak moves to lower energies when the bias voltage decreases VERTEX 2006

  26. Fe-55 Image The matrix was tuned, mean threshold at about 830 e Shadow of a wire Shadow of a micrometer VERTEX 2006

  27. Co-60 Irradiation Pixels at the matrix edges sense more signals than the inner pixels VERTEX 2006

  28. Summary • The idea: • The use of reverse biased N-well/P-substrate diode as sensor • Depleted zone of ~ 9 m can be induced by applying of relatively high bias voltage • CMOS pixel electronics can been implemented in the sensor cathode (N-well) • The first test-chip have been implemented in a 0.35 m HV CMOS Process • The pixel electronics comprises • Charge sensitive amplifier and CR-RC shaper • Continuous reset and bias • Threshold discrimination with 4-bit tune DAC • NMOS-based latch and bus driver • Various electrical test demonstrate fully functionality of the detector • The average MIP signal estimated from the measurements with Sr-90 radioactive sources is 1710 e – it is by far more than expected; probably due to collection of the signal from bulk • Noise is about 80 e • Threshold dispersion is 75 e • Test-beam measurement has to be done; from the presented results I expect good efficiency of the detector • New submission with different test matrices is planned VERTEX 2006

  29. Thank you for your attention VERTEX 2006

  30. Future Plans (pulsed Reset and DKS) Reset Sample CSA CSA Readout Bus TCA AC Coupling Simpler designs, which lead to smaller detector capacitance, has to be tested VERTEX 2006

  31. Standard MAPS • The use of epi layer (or low-ohmic substrate) as sensor • - Charge collection mainly through diffusion • - very low sensor capacitance • Only NMOS transistors in the pixel Amplified signal N-well Epi-layer Substrate VERTEX 2006

  32. Triple-Well MAPS • The use of epi layer (or low-ohmic substrate) as sensor and deep N-well as collecting electrode • - Charge collection mainly through diffusion • - Higher sensor capacitance • CMOS electronics in pixel… • but PMOS transistors are placed in the separate N-well N-well Epi-layer Substrate VERTEX 2006

  33. MAPS in HV Technology • The use of high-voltage N-well/P-substrate diode as sensor • - Relatively large depleted zone with strong electric field • - Efficient charge collection • - Fast signals • - Better radiation tolerance • Fully implementation of CMOS electronics inside the sensor cathode thanks to triple well option • - Large cathode area but… • moderate capacitance due to thick depleted areas VERTEX 2006

  34. Capacitances - Simulation This can be potentially useful! VERTEX 2006

  35. Small-Signal Measurements Time over threshold distribution after many injections Regular pixel, 600 e Diode, 360 e VERTEX 2006

  36. Noise Specification Undetected Signal 6 noise + 6 threshold Signal Amplitude Noise Too high threshold Threshold j Threshold i Threshold Dispersion Too low threshold Noise Base Line Noise Hit 6 noise + 6 threshold < Signal VERTEX 2006

  37. Hit Multiplicity Larger range of Co-60 signals respecting to Fe-55 VERTEX 2006

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