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Recent progress in the Development of a B-Factory Monolithic Active Pixel Detector

Recent progress in the Development of a B-Factory Monolithic Active Pixel Detector. Samo Stani č for the Belle Pixel Group H. Aihara 5 , M . Barbero 1 , A. Bozek 4 , T. Browder 1 , M. Hazumi 3 , J. Kennedy 1 ,

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Recent progress in the Development of a B-Factory Monolithic Active Pixel Detector

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  1. Recent progress in the Development of aB-Factory Monolithic Active Pixel Detector Samo Stanič for the Belle Pixel Group H. Aihara5, M. Barbero1, A. Bozek4, T. Browder1, M. Hazumi3,J. Kennedy1, N. Kent1, S. Olsen1, H. Palka4, M. Rosen1, L. Ruckman1, S. Stanič2,K. Trabelsi1,T. Tsuboyama3, K. Uchida1, G. Varner1 and Q. Yang1 1University of Hawaii, USA, 2Nova Gorica Polytechnic, Slovenia, 3 High Energy Accelerator Research Organization (KEK), Japan, 4 H. Niewondiczanski Institute of Nuclear Physics, Poland, 5University of Tokyo, Japan 10th European Symposium on Semiconductor Detectors Wildbad Kreuth, 2005/06/13

  2. Mt.Tsukuba KEKB Belle ~1 km indiameter Belle Experiment at KEKB Collider KEKB / Belle started operation in 1999 Belle detector 8 GeV e- x 3.5 GeV e+ Aerogel Cherenkov cnt. n=1.015~1.030 SC solenoid 1.5T L peak > 1.5 x 1034 cm-2 sec-1 (world record peak luminosity) CsI(Tl) 16X0 3.5 GeV e+ TOF counter Central Drift Chamber small cell +He/C2H5 8 GeV e- m / KL detection 14/15 lyr. RPC+Fe Silicon Vertex Detector Recorded integrated luminosity of about 400 fb-1 !

  3. Motivation ~10% ~4% ~2% ~2% SuperKEKB luminosity increase: L~1.5 x 1034 → L~5 x 1035 cm-2.s-1 Conventional solutions (Si strips) will not work… 2. Improvement of impact parameter resolution Present Belle SVD2 1. Reduce SVD occupancy Present : layer 1 of SVD ~10%occupancy / 200 Krad.yr-1 Upgrade: Super-Belle ~ 20 – 50 x(?) expectedbackground increase

  4. Natural alternative - Pixel type sensor Requirements R&D steps • Low occupancy • Fast Readout Speed • Radiation Hardness • Thin Sensor • Full-sized detector prototype Technology Choice XTEST2, LHC hybrid pixels MAPS CAP1 – basic functionality Jun. 2004 @ KEK Prototypes CAP2 – pipelined readout T943 Dec. 2004 @ FNAL CAP3 – full-size/speed Autumn 2005 (expected) Preliminary Design Report • Near Term (SVD2 Layer 1 drop-in) • IR upgrade PVD1.0

  5. Belle Pixel Sensor Evolution CAP1 CAP3 CAP2 PVD1.0 full-size/speed basic functionality time 2004 2005 2003 final detector technology choice pipelined readout

  6. Candidate: Monolithic Active Pixel Sensor Current DSSD MAPS 10mm 300mm • Key Features • Thermal charge collection (no HV) • Thin - reduced multiple-scattering, g conversion, background g target • NO bump bonding – fine pitch possible (8000x geometrical reduction) • Standard CMOS process - “System on Chip” possible Because of large capacitance, need for thick DSSDs -- MAPS can be made VERY thin

  7. Continuous Acquisition Pixel (CAP) Concept V_Q_integr Based on 3 transistor cell Vreset Vdd Vdd Source follower buffering of collected charge Δvtyp α Ileak Reset M1 Δvsig α Qsignal M2 Collection Electrode M3 Row Bus Output time Integration time reset Gnd tfr1 tfr2 ADC Restores potential to collection electrode High-speed Array of pixels Analog read-out Pixel & storage Low power – only significant draw at readout edge Pixel Array: Column select – ganged row read

  8. Correlated Double Sampling (CDS) ( - ) 8ms integration Frame 1 - Frame 2 = Can readout/process @ 20Hz ~ 16% live time (CAP1!) Self-Triggering mode - Leakage current Correction ~fA leakage current (typ) ~18fA for hottest pixel shown Hit candidate!

  9. CAP1: basic operation confirmedin a beam-test experiment The 4 F2 boards Pixel chip: 132x48=6336 channels X-Y stages Pion Beam All LVDS digital I/O 300-600Mbaud link ~1mm x 3mm On board ADC

  10. CAP1/2 system overview Front-End board Power supply & control lines (LVDS, RJ45) CTRL Test pixel in 48→12 MUX 132 col 48 row 1 serial signal (LVDS, RJ45) Serializer ADC CAP Marker Back-End board Highlights: Front-End board: MUX, ADC, serializer, CPLD Back-End board: cPCI RAM, 5 CPLDs, CPU BUS CPU F2 BUF RAM CTRL F2 4 Front-End boards RAM BUF Data Acquistion F2 BUF RAM F2 BUF RAM

  11. Correlated hits in all 4 layers

  12. Hit resolution measurement 1mm Alumina substrate 250mm Si 1mm plastic 3.4 cm 4.6 cm 3.6 cm L2 L4 L3 (in mm) z-plane x-plane (in mm) “hit” Residuals for 4GeV/c pions: < 11mm (in both planes)

  13. Radiation damage Belle CAP1 Prototype Fully annealed IEEE Trans. Nucl. Sc. 48, 1796-1806,2001

  14. Peak pixel S/N prediction Extrapolation from upper edges of Eid et al.

  15. CAP2 – Pipelined operation TSMC 0.35mm 132 x 48 8 deep mini-pipeline in each cell 3-transistor cell 132x48=6336 channels 50688 samples 10msframe acquisition speed achieved! Pixel size 22.5mmx 22.5mm

  16. CAP3 – Full scale pipelined prototype TSMC 0.25mm Process 5-deep double pipeline 36 transistors/pixel 5 metal layers 5 sets CDS pairs

  17. CAP3 - sensor layout 21 mm Active area 20.88 mm 3 mm >93% active without active edge processing 928 x 128 pixels = 118,784 ~4.3M transistors !

  18. CAP3 readout Ampl ADC/LVDS CAP3 CAP3 Bonds • Laboratory testing of the F3 frontend readout board is under way • Working on the firmware F3 board

  19. System setup for CAP3 sensor BE CAP3 MC1 card F3 Serialized data out from the MC1 card and control signals to the MC1 card through RJ-45 connectors. MOBCADS

  20. CAP3 DAQ New CPU card for DAQ: from aslow 300 MHz PIII processor for CAP1/CAP2 to 2.2 GHz Pentium4 and neat 2.5” 100Gbon-board disk(using Fedora Core 3 ) →boost to the data acquisition. RAM 100GB disk 2.2GHz P4

  21. CAP3 system overview CAP3 Front-End Board Scintillator+ PMT Scintillator+ PMT Ampl Reg ADC/LVDS Mother Board (16) (16) RAM Master FPGA PROM RJ45 To/from Back-End Board Mezzanine Card LVDS Tx/Rx Serial All these components sit on movable table

  22. CAP3 based full detector concept Half ladder scheme CAP3 Pixel Readout Board (PROBE) 5-layer flex PIXRO1 chip 128 x 928 pixels, 22.5mm2 ~120 Kpixels / CAP3 0.25 mm process End view Side view Double layer, offset structure Length: 2x21mm ~ 4cm r~8mm r~8mm 17o 30o e- e+ # of Detector / layer ~ 32

  23. “Fast” Belle SVD2 L1 upgrade option ~10% ~4% ~2% ~2% Replace Layer 1 with CAP3 pixels Mechanically identical (drop in) CAP3 Flex

  24. Belle SVD L1 upgrade Flex CAP3 4 x 9 = 36 CAP3 / L1 ladder 6 ladders/L1 layer ~26M Channels total Scaling current SVD L1 * 4 background ~ few kBytes/event R=7mm configuration: 6.6M channels SVD L1 * 40 background ~ few 100kBytes/event With L3 track match: ~few 10kBytes/event

  25. Summary: Critical R&D Milestones • Readout Speed • Radiation Hardness • Thin Detector • Full-sized detector 100kHz frame rate, 10kHz L2 accept 10ms frame acquisition OK (CAP2), CAP3 to test 100ms frame readout >= 20MRad Leakage current OK (CAP2), q collection efficiency TBD <= 50mm, double layer 50mm mechanical dummies, CAP3 to be thinned (SNF) Span acceptance (reticle limit) CAP3 fabricated – performance evaluation under way

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