ELEC 7770 Advanced VLSI Design Spring 2010 Logic Synthesis

1. ELEC 7770Advanced VLSI DesignSpring 2010 Logic Synthesis Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr10 ELEC 7770: Advanced VLSI Design (Agrawal)

2. Logic Synthesis • Definition: To design a logic circuit such that it meets the specifications and can be economically manufactured: • Performance – meets delay specification, or has minimum delay. • Cost – uses minimum hardware, smallest chip area, smallest number of gates or transistors. • Power – meets power specification, or consumes minimum power. • Testablility – has no redundant (untestable) logic and is easily testable. ELEC 7770: Advanced VLSI Design (Agrawal)

3. Synthesis Procedure • Minimization – Obtain MSOP or MPOS. This is also known as two-level minimization because the result can be implemented as a two-level AND-OR or NAND-NAND or NOR-NOR circuit. • Technology mapping – Considering design requirements, transform the minimized form into one of the technologically realizable forms: • Programmable logic array (PLA) • Standard cell library • Field programmable gate array (FPGA) • Other . . . ELEC 7770: Advanced VLSI Design (Agrawal)

4. References on Synthesis G. De Micheli, Synthesis and Optimization of Digital Circuits, New York: McGraw-Hill, 1994. S. Devadas, A. Ghosh and K. Keutzer, Logic Synthesis, New York: McGraw-Hill, 1994. ELEC 7770: Advanced VLSI Design (Agrawal)

5. Programmable Logic Array (PLA) • A direct implementation of multi-output function as a two-level circuit in MOS technology. • PLA styles: • NAND-NAND • NOR-NOR ELEC 7770: Advanced VLSI Design (Agrawal)

6. Example: Two-Output Function F1 A F2 A D D C C B B Need four products: P1, P2, P3, P4 ELEC 7770: Advanced VLSI Design (Agrawal)

7. Two-Level AND-OR Implementation INPUTS AND OR C P1 F1 P2 A P3 F2 B P4 D Also known as technology-independent circuit. ELEC 7770: Advanced VLSI Design (Agrawal)

8. NAND-NAND Implementation INPUTS NAND NAND C F1 A F2 B D ELEC 7770: Advanced VLSI Design (Agrawal)

9. A NAND Gate in MOS Technology VDD VDD VDD XY XY XY X X X Y Y Y GND GND GND R. C. Jaeger and T, N. Blalock, Microelectronic Circuit Design, Boston: McGraw-Hill, 2008, Section 6.8.2. ELEC 7770: Advanced VLSI Design (Agrawal)

10. NAND-NAND PLA A B C D F1 F2 VDD VDD VDD VDD VDD VDD GND ELEC 7770: Advanced VLSI Design (Agrawal)

11. NAND-NAND PLA SCHEMATIC A B C D F1 F2 INPUTS OUTPUTS AND-plane OR-plane ELEC 7770: Advanced VLSI Design (Agrawal)

12. Standard-Cell Design • Obtain two-level minimized form. • Map the design onto predesigned building blocks called standard cells (technology mapping). • Standard-cell library contains predesigned logic cells in the technology of manufacture. Examples of technology: • 90 nanometer CMOS • 65 nanometer CMOS • 45 nanometer CMOS • . . . • This is known as application-specific integrated circuit (ASIC). ELEC 7770: Advanced VLSI Design (Agrawal)

13. Technology Mapping Find a common logic elements, e.g., two-input NAND gate and inverter. MSOP is converted into NAND-NAND circuit. Split gates into library cells, two-input NAND gates and inverters. Cover the circuit with standard cells, also split into two-input NAND gates and inverters (graph-matching). ELEC 7770: Advanced VLSI Design (Agrawal)

14. A Typical Cell Library S. Devadas, A. Ghosh and K. Keutzer, Logic Synthesis, New York: McGraw-Hill 1994, Section 7.7, pp. 185-198. ELEC 7770: Advanced VLSI Design (Agrawal)

15. NAND3 Cell Directed Acyclic Graph (DAG) (tree) ELEC 7770: Advanced VLSI Design (Agrawal)

16. NAND4 Cell ELEC 7770: Advanced VLSI Design (Agrawal)

17. AOI21 Cell ELEC 7770: Advanced VLSI Design (Agrawal)

18. OAI21 Cell ELEC 7770: Advanced VLSI Design (Agrawal)

19. AOI22 Cell ELEC 7770: Advanced VLSI Design (Agrawal)

20. XOR Cell ELEC 7770: Advanced VLSI Design (Agrawal)

21. Technology Mapping Procedure Obtain MSOP. Convert to two-level AND-OR circuit. Transform to two-level NAND-NAND circuit. Transform to two-input NAND and inverter tree network. Perform an optimal pattern matching to obtain a minimum cost tree covering. ELEC 7770: Advanced VLSI Design (Agrawal)

22. Previous Example: 2-Level NAND INPUTS NAND NAND C F1 A F2 B D ELEC 7770: Advanced VLSI Design (Agrawal)

23. Circuit is a Directed Acyclic Graph (DAG) C F1 A F2 B Each node is a NAND gate. D ELEC 7770: Advanced VLSI Design (Agrawal)

24. Splitting into a Forest of Trees C F1 D B C D A F2 B A D ELEC 7770: Advanced VLSI Design (Agrawal)

25. Splitting DAG into Trees (Forest) C D F1 C B D A B F2 A D ELEC 7770: Advanced VLSI Design (Agrawal)

26. A Simple Technology Mapping NAND2 (3) NAND2 (3) (2) C F1 D NAND3 (4) NAND3 (4) B (2) F2 NAND2 (3) A Cost = 24 NAND2 (3) ELEC 7770: Advanced VLSI Design (Agrawal)

27. Two-Input NAND Trees C F1 D B C D A F2 B A D ELEC 7770: Advanced VLSI Design (Agrawal)

28. Alternatively, in Graph Format C D F1 B C D A F2 B A D ELEC 7770: Advanced VLSI Design (Agrawal)

29. An Improved Technology Mapping C OAI21 (4) D F1 (2) (2) Inverters inserted For pattern matching B NAND3 (4) C D NAND3 (4) A F2 B (2) NAND2 (3) A Cost = 22 D NAND2 (3) ELEC 7770: Advanced VLSI Design (Agrawal)

30. Alternatively, in Graph Format C OAI21 (4) D F1 (2) Nodes inserted For pattern matching B NAND3 (4) C D Cost = 22 NAND3 (4) NAND2 (3) A F2 B (2) A D NAND2 (3) ELEC 7770: Advanced VLSI Design (Agrawal)

31. Improved Technology Mapping C AOI21 (4) F1 (2) D NAND3 (4) NAND3 (4) B (2) F2 NAND2 (3) A Cost = 22 NAND2 (3) ELEC 7770: Advanced VLSI Design (Agrawal)

32. Original Reference K. Keutzer, “DAGON: Technology Binding and Local Optimization by DAG Matching,” Proc.24th Design Automation Conf., 1987, pp. 341-347. ELEC 7770: Advanced VLSI Design (Agrawal)